Abstract: A dynamic random access memory device includes a storage capacitor having a plurality of stacked conductive films which form a storage electrode. A gap is formed between elevationally adjacent conductive films so as to surround the storage electrode. A gap is also formed between an insulating film which covers a gate electrode for insulation and a lowermost film of the storage electrode. Connection between the adjacent films may be established so that an uppermost film elevationally extends so as to make contact with a drain region. Also, connection can be established so that an upper film is mounted directly on an lower film. An end portion of the film may be thicker than the other portion thereof. The stacked film structure may be produced by alternatively forming a film made of a material different from the insulating film covering the gate electrode, and a conductive film.

Abstract: A dynamic random access memory includes a semiconductor substrate having an active region including first and second diffusion regions of a transfer transistor, an insulating layer formed on the semiconductor substrate and having first and second contact holes, and a stacked capacitor having a storage electrode which is electrically coupled to the first diffusion region through the first contact hole formed in the insulating layer and an opposed electrode. The DRAM also includes a word line electrically isolated from the semiconductor substrate, and a bit line electrically isolated from the semiconductor substrate and electrically coupled to the second diffusion region through the second contact hole formed in the insulating layer. The second contact hole is substantially positioned at a center of the bit line. The word line has a bent portion located between the first and second contact holes so that the word line is separated from the second contact hole at a predetermined distance.

Abstract: A CMOS inverter which comprises a series of connected p-channel and n-channel MOS FETs of which gate electrodes, drain contact electrodes, and voltage source lines are arranged on different insulation layers stacked on each other. The drain contact electrodes are formed by a conductor, including a silicide of high melting point metal, such as, tungsten or molybdenum. They are coated by an insulation layer over which the voltage source lines and signal lines for transferring output to a succeeding stage are arranged. By doing so, the device area is decreased, and the substrate can be reflowed to smooth the surface of the insulator so as to prevent disconnecting of the wirings.

Abstract: A static random access memory device including resistance loaded flip-flop circuits has adjacent memory cells arranged to form memory cell pairs. Each memory cell pair has a first unit cell and a second unit cell. Load resistors for the first unit cells and load resistors for the second unit cells are formed on different insulation layers and are stacked on each other on the substrate. A structural pattern of the load resistors is extended over adjacent memory cells in order for the length and resistance of the resistors to be increased. The length of the load resistors can be cut down for compensating for the increase in the resistance enabling the reduction in size of other devices, and enabling the packing density of the device to be increased.

Abstract: A method of producing a layer structure of a memory cell for dynamic random access memory device includes the steps of forming an insulation film on a semiconductor substrate, forming a first conductive film on the insulation film, the first conductive film being used for forming a part of a storage electrode of a memory cell capacitor, patterning the first conductive film and the insulation film so as to form a window used for forming a contact between the storage electrode and the semiconductor substrate, forming a second conductive film so as to cover the window and the first conductive film, the second conductive film being used for forming the remaining part of the storage electrode, and patterning the first conductive film and the second conductive film, patterened first and second conductive films constructing the storage electrode, forming a dielectric film so as to cover the storage electrode, and forming a third conductive film so as to cover the dielectric film, the third conductive film being an o

Abstract: A semiconductor memory device includes a plurality of bit lines formed on an interlayer insulation film and arranged with a first pitch defining a distance between neighboring bit lines, and word lines which are formed on an insulation film formed on the bit lines and which are arranged with a second pitch defining a distance between neighboring word lines. One of the bit and word lines which has a relatively wide pitch comprises an aluminum-based metallization film, and the other line which has a relatively narrow pitch comprises a refractory metal silicide-based metallization film.

Abstract: A dynamic random access memory device includes a storage capacitor having a plurality of stacked conductive films which form a storage electrode. A gap is formed between elevationally adjacent conductive films so as to surround the storage electrode. A gap is also formed between an insulating film which covers a gate electrode for insulation and a lowermost film of the storage electrode. Connection between the adjacent films may be established so that an uppermost film elevationally extends so as to make contact with a drain region. Also, connection can be established so that an upper film is mounted directly on a lower film. An end portion of the film may be thicker than the other portion thereof. The stacked film structure may be produced by alternatively forming a film made of a material different from the insulating film covering the gate electrode, and a conductive film.

Abstract: A semiconductor memory device includes a semiconductor substrate having source and drain regions each having a conduction type opposite to that of the semiconductor substrate, an insulation film formed on a main surface of the semiconductor substrate having first and second contact windows, and a gate electrode formed on the insulation film so as to be located between the source and drain regions. The semiconductor substrate has a charge barrier layer which has the same conduction type as the semiconductor substrate and which has an impurity concentration higher than that of the semiconductor substrate. The charge barrier layer is formed so that a depth (d.sub.1) of the charge barrier layer located under the gate electrode measured from the main surface of the semiconductor substrate is smaller than a depth (d.sub.2) of the charge barrier layer located under the source and drain regions measured from the main surface of the semiconductor substrate.

Abstract: A Dynamic Random Access Memory device includes bit lines formed on an interlayer insulation film which covers gate electrodes on an insulation film on a semiconductor substrate. Each bit line is in contact with the corresponding source region formed in the substrate through an opening in the insulation films. Another insulation film is formed so as to cover the bit lines. A storage electrode is formed on the insulation film covering the bit line, and is in contact with a drain region in the substrate through another opening in the insulation films. The bit line has a vertical layer level lower than that of the storage electrode. The storage electrode is covered with a dielectric film, which is covered with an opposed electrode.

Abstract: A semiconductor memory device includes a memory cell portion and a peripheral circuit portion which are provided on a silicon substrate. The peripheral circuit portion includes an insulation film having a contact hole formed on the silicon substrate, a barrier layer formed in the contact hole having a layer structure which is the same as that of a metallization film provided in the memory cell portion and which is formed at the same time as forming the first metallization film. The above layer structure includes a polysilicon film and a metal silicide film. A metallization film of an alloy of aluminum and silicon overlies the barrier layer in the contact hole.

Abstract: A layer structure of a memory cell for a dynamic random access memory device includes a semiconductor substrate, an insulation film formed on the semiconductor substrate having a first window through which a surface of the semiconductor substrate is partially exposed, a first conductive film formed on the insulation film so as to surround the contact window and form a second window above the first window, a second conductive film formed so as to be in contact with the first conductive film, and the semiconductor substrate through the first and second windows, the first and second conductive films constructing a storage electrode of a memory cell capacitor, a dielectric film formed so as to cover the storage electrode; and a third conductive film formed so as to cover the dielectric film.

Abstract: A semiconductor memory device including a plurality of stacked-capacitor type memory cells, each having a capacitor storing data and a transfer-gate transistor transferring data to the capacitor. The transistor includes a gate connected to a word line and formed by an insulating layer, and source and drain regions. Each of the memory cells has a first insulating layer covering the gate of the transfer-gate transistor.The capacitor in each memory cell includes a second insulating layer covering another word line adjacent to the one word line and having a larger thickness perpendicular to a plane of a substrate than that of the first insulating layer covering the gate, a second conductive layer which is in contact with one of the source and drain regions of the transistor, extends over the gate through the first insulating layer and covers the second insulating layer, a third insulating layer formed on the second conductive layer, and a third conductive layer extending over the third insulating layer.

Abstract: In a memory cell matrix region of a semiconductor memory device such as a dynamic RAM or a static RAM, wirings of the same material are distributed between different layers in such a manner that the upper wirings overlap the lower wirings. Accordingly, the width of the wirings can be increased for a semiconductor memory device having a high concentration and high integration.

Abstract: A method of fabricating a narrow channel width IG-FET which includes compensating for impurities diffused into the channel region from the channel stopper, thereby providing the IG-FET with a threshold providing the IG-FET with a threshold voltage establishing at a level substantially the same as that of conventional wider channel width IG-FETs. According to the present invention, impurities having a conductivity type opposite to that of the impurities diffused from the channel stopper are selectively implanted in at least the channel region of the narrow channel width IG-FET, to compensate the diffused impurities. Impurities for channel doping are then implanted to adjust the threshold voltage.