Abstract: A semiconductor device includes a gate electrode formed on a semiconductor region via a gate insulative film and an extension high concentration diffusion layer of a first conductivity type formed in the semiconductor region beside the gate electrode. A dislocation loop defect layer is formed in a region of the semiconductor region beside the gate electrode and at a position shallower than an implantation projected range of the extension high concentration diffusion layer.

Abstract: An n-type channel diffused layer and an n-type well diffused layer are formed in the top portion of a semiconductor substrate, and a gate insulating film and a gate electrode are formed on the semiconductor substrate. Using the gate electrode as a mask, boron and arsenic are implanted to form p-type extension implanted layers and n-type pocket impurity implanted layers. Fluorine is then implanted using the gate electrode as a mask to form fluorine implanted layers. The resultant semiconductor substrate is subjected to rapid thermal annealing, forming p-type high-density extension diffused layers and n-type pocket diffused layers. Sidewalls and p-type high-density source/drain diffused layers are then formed.

Abstract: Between a source/drain heavily-doped diffusion layer and a region below a side face of a gate electrode in an epitaxial semiconductor substrate, an extension heavily-doped diffusion layer where N-type As ions are diffused is formed to have shallower junction than the source/drain heavily-doped diffusion layer. A pocket heavily-doped diffusion layer where P-type indium ions, that is, heavy ions having a relatively large mass number, are diffused is formed under the extension heavily-doped diffusion layer.

Abstract: Into a channel formation region of a semiconductor substrate of p-type silicon, indium ions are implanted at an implantation energy of about 70 keV and a dose of about 5×1013/cm2, thereby forming a p-doped channel layer. Next, germanium ions are implanted into the upper portion of the semiconductor substrate at an implantation energy of about 250 keV and a dose of about 1×1016/cm2, thereby forming an amorphous layer in a region of the semiconductor substrate deeper than the p-doped channel layer.

Abstract: Between a source/drain heavily-doped diffusion layer and a region below a side face of a gate electrode in an epitaxial semiconductor substrate, an extension heavily-doped diffusion layer where N-type As ions are diffused is formed to have shallower junction than the source/drain heavily-doped diffusion layer. A pocket heavily-doped diffusion layer where P-type indium ions, that is, heavy ions having a relatively large mass number, are diffused is formed under the extension heavily-doped diffusion layer.

Abstract: As impurity ions for forming a channel, heavy ions are implanted multiple times at a dose such that no dislocation-loop defect layer is caused to be formed, and an annealing process is performed after each ion implantation process has been carried out, thereby forming a heavily doped channel layer having a steep retro-grade impurity profile.

Abstract: A semiconductor device includes a gate electrode formed on a semiconductor region via a gate insulative film and an extension high concentration diffusion layer of a first conductivity type formed in the semiconductor region beside the gate electrode. A dislocation loop defect layer is formed in a region of the semiconductor region beside the gate electrode and at a position shallower than an implantation projected range of the extension high concentration diffusion layer.

Abstract: As impurity ions for forming a channel, heavy ions are implanted multiple times at a dose such that no dislocation-loop defect layer is caused to be formed, and an annealing process is performed after each ion implantation process has been carried out, thereby forming a heavily doped channel layer having a steep retro-grade impurity profile.

Abstract: After a gate electrode has been formed over a semiconductor region with a gate insulating film interposed therebetween, an amorphous layer is formed in the semiconductor region by implanting heavy ions with a large mass into the semiconductor region using the gate electrode as a mask. Then, ions of a first dopant are implanted into the semiconductor region using the gate electrode as a mask. Next, a first annealing process is conducted on the semiconductor region at a temperature between 400° C. and 550° C., thereby making the amorphous layer recover into a crystalline layer. Subsequently, a second annealing process is conducted on the semiconductor region, thereby forming an extended high-concentration dopant diffused layer of a first conductivity type and a pocket dopant diffused layer of a second conductivity type.

Abstract: A semiconductor device includes a gate electrode formed on a semiconductor region via a gate insulative film, and an extension high concentration diffusion layer of a first conductivity type formed in the semiconductor region beside the gate electrode. A dislocation loop defect layer is formed in a region of the semiconductor region beside the gate electrode and at a position shallower than an implantation projected range of the extension high concentration diffusion layer.

Abstract: Between a source/drain heavily-doped diffusion layer and a region below a side face of a gate electrode in an epitaxial semiconductor substrate, an extension heavily-doped diffusion layer where N-type As ions are diffused is formed to have shallower junction than the source/drain heavily-doped diffusion layer. A pocket heavily-doped diffusion layer where P-type indium ions, that is, heavy ions having a relatively large mass number, are diffused is formed under the extension heavily-doped diffusion layer.