Patents by Inventor Taimi Oketani

Taimi Oketani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11054695
    Abstract: A chip-mounted board including: micro light-emitting chips arranged in a matrix pattern in a light-emitting region; and a conductive line electrically connected to the micro light-emitting chips, the light-emitting region including a first region having a first luminance, a second region having a second luminance lower than the first luminance, and a third region having a third luminance lower than the first luminance and higher than the second luminance, the luminances being values determined with the same magnitude of current supplied to the micro light-emitting chips, the third region being positioned between the first region and the second region and satisfying the following formulas (1) and (2): (1+k)/(1?k)?63.895×tan(0.5°)×500/W+6.0525??(1) L2=k×L1??(2) wherein L1 represents the first luminance, L2 represents the second luminance, and W represents a width (unit: mm) of the third region.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: July 6, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Taimi Oketani, Atsushi Ban, Yasuhisa Itoh, Takeshi Ishida
  • Patent number: 10866461
    Abstract: In an image display device including an image taking window portion, the image taking window portion for an image taking camera is disposed within the image display region, and an outer diameter of a frame portion is set to satisfy a specific condition based on an angle of view of the image taking camera.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: December 15, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Jin Nakamura, Kohhei Katsuya, Taimi Oketani, Yoshihito Ishizue
  • Publication number: 20200292882
    Abstract: In an image display device including an image taking window portion, the image taking window portion for an image taking camera is disposed within the image display region, and an outer diameter of a frame portion is set to satisfy a specific condition based on an angle of view of the image taking camera.
    Type: Application
    Filed: March 11, 2020
    Publication date: September 17, 2020
    Inventors: JIN NAKAMURA, KOHHEI KATSUYA, TAIMI OKETANI, YOSHIHITO ISHIZUE
  • Publication number: 20200019016
    Abstract: A chip-mounted board including: micro light-emitting chips arranged in a matrix pattern in a light-emitting region; and a conductive line electrically connected to the micro light-emitting chips, the light-emitting region including a first region having a first luminance, a second region having a second luminance lower than the first luminance, and a third region having a third luminance lower than the first luminance and higher than the second luminance, the luminances being values determined with the same magnitude of current supplied to the micro light-emitting chips, the third region being positioned between the first region and the second region and satisfying the following formulas (1) and (2): (1+k)/(1?k)?63.895×tan(0.5°)×500/W+6.0525??(1) L2=k×L1??(2) wherein L1 represents the first luminance, L2 represents the second luminance, and W represents a width (unit: mm) of the third region.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 16, 2020
    Inventors: Taimi Oketani, Atsushi Ban, Yasuhisa Itoh, Takeshi Ishida
  • Patent number: 10310347
    Abstract: There are provided a display apparatus and a method of manufacturing the display apparatus. The display apparatus includes a pixel having a first thin film transistor and a drive circuit having a second thin film transistor and driving the pixel, wherein a first channel region of the first thin film transistor and a second channel region of the second thin film transistor are configured to have different electrical characteristics (for example, electron mobility, thereby enabling the first thin film transistor and the second thin film transistor to function suitably for the each role thereof).
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: June 4, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Shigeru Ishida, Nobutake Nodera, Ryouhei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Patent number: 10243003
    Abstract: The thin film transistor includes: a gate electrode formed on a surface of a substrate; a polysilicon layer formed on an upper side of the gate electrode; an amorphous silicon layer formed on the polysilicon layer so as to cover the same; an n+ silicon layer formed on an upper side of the amorphous silicon layer; and a source electrode and a drain electrode which are formed on the n+ silicon layer, wherein, in a projected state in which the polysilicon layer, the source electrode and the drain electrode are projected onto the surface of the substrate, a part of the polysilicon layer and a part of each of the source electrode and the drain electrode are adapted so as to be overlapped with each other, and in the projected state, a minimum dimension, in a width direction orthogonal to a length direction between the source electrode and the drain electrode, of the polysilicon layer located between the source electrode and the drain electrode is smaller than dimensions in the width direction of the source electrod
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: March 26, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Nobutake Nodera, Shigeru Ishida, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Patent number: 10038098
    Abstract: The method for manufacturing a thin film transistor includes the processes of forming a gate electrode on a surface of a substrate, forming an insulation film on the surface of the substrate on which the gate electrode is formed, forming a first amorphous silicon layer on the surface of the substrate on which the insulation film is formed, annealing a plurality of required places separated from each other on the first amorphous silicon layer by irradiating the same with an energy beam to change the required places to a polysilicon layer, forming a second amorphous silicon layer by covering the polysilicon layer, forming an n+ silicon layer on a surface of the second amorphous silicon layer, etching the first amorphous silicon layer, the second amorphous silicon layer and the n+ silicon layer.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: July 31, 2018
    Assignee: Sakai Display Products Corporation
    Inventors: Nobutake Nodera, Shigeru Ishida, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Publication number: 20180196294
    Abstract: There are provided a display apparatus and a method of manufacturing the display apparatus. The display apparatus includes a pixel having a first thin film transistor and a drive circuit having a second thin film transistor and driving the pixel, wherein a first channel region of the first thin film transistor and a second channel region of the second thin film transistor are configured to have different electrical characteristics (for example, electron mobility, thereby enabling the first thin film transistor and the second thin film transistor to function suitably for the each role thereof).
    Type: Application
    Filed: March 9, 2018
    Publication date: July 12, 2018
    Inventors: Shigeru Ishida, Nobutake Nodera, Ryouhei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Patent number: 10008606
    Abstract: The thin film transistor includes a gate electrode formed on a surface of a substrate; a first amorphous silicon layer formed on an upper side of the gate electrode; a plurality of polysilicon layers separated by the first amorphous silicon layer and formed on the upper side of the gate electrode with a required spaced dimension; a second amorphous silicon layer and an n+ silicon layer which are formed on the upper side of the plurality of polysilicon layers and the first amorphous silicon layer; and a source electrode and a drain electrode formed on the n+ silicon layer.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: June 26, 2018
    Assignee: Sakai Display Products Corporation
    Inventors: Shigeru Ishida, Nobutake Nodera, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Publication number: 20180097120
    Abstract: The thin film transistor includes a gate electrode formed on a surface of a substrate; a first amorphous silicon layer formed on an upper side of the gate electrode; a plurality of polysilicon layers separated by the first amorphous silicon layer and formed on the upper side of the gate electrode with a required spaced dimension; a second amorphous silicon layer and an n+ silicon layer which are formed on the upper side of the plurality of polysilicon layers and the first amorphous silicon layer; and a source electrode and a drain electrode formed on the n+ silicon layer.
    Type: Application
    Filed: March 30, 2015
    Publication date: April 5, 2018
    Inventors: Shigeru Ishida, Nobutake Nodera, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Publication number: 20170162709
    Abstract: The method for manufacturing a thin film transistor includes the processes of forming a gate electrode on a surface of a substrate, forming an insulation film on the surface of the substrate on which the gate electrode is formed, forming a first amorphous silicon layer on the surface of the substrate on which the insulation film is formed, annealing a plurality of required places separated from each other on the first amorphous silicon layer by irradiating the same with an energy beam to change the required places to a polysilicon layer, forming a second amorphous silicon layer by covering the polysilicon layer, forming an n+ silicon layer on a surface of the second amorphous silicon layer, etching the first amorphous silicon layer, the second amorphous silicon layer and the n+ silicon layer.
    Type: Application
    Filed: November 7, 2014
    Publication date: June 8, 2017
    Inventors: Nobutake Nodera, Shigeru Ishida, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Publication number: 20170154901
    Abstract: The thin film transistor includes: a gate electrode formed on a surface of a substrate; a polysilicon layer formed on an upper side of the gate electrode; an amorphous silicon layer formed on the polysilicon layer so as to cover the same; an n+ silicon layer formed on an upper side of the amorphous silicon layer; and a source electrode and a drain electrode which are formed on the n+ silicon layer, wherein, in a projected state in which the polysilicon layer, the source electrode and the drain electrode are projected onto the surface of the substrate, a part of the polysilicon layer and a part of each of the source electrode and the drain electrode are adapted so as to be overlapped with each other, and in the projected state, a minimum dimension, in a width direction orthogonal to a length direction between the source electrode and the drain electrode, of the polysilicon layer located between the source electrode and the drain electrode is smaller than dimensions in the width direction of the source electrod
    Type: Application
    Filed: March 27, 2015
    Publication date: June 1, 2017
    Applicant: Sakai Display Products Corporation
    Inventors: Nobutake Nodera, Shigeru Ishida, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Publication number: 20130235278
    Abstract: A method of manufacturing a liquid crystal panel in which the bright point defect is effectively corrected is provided. The method of manufacturing a liquid crystal panel 11 including a pair of substrates 40 and 30, and a liquid crystal layer 50 provided between the pair of the substrates 40 and 30 includes detecting a bright point defect in the liquid crystal panel 11; forming a first light blocking portion BL1 in one of the substrates 40 and 30 and in a part of an area that surrounds the bright point defect with a plan view; forming a recess in a portion of one of the substrates 40, 30 that overlaps the bright point defect and on a surface of the one of the substrates 40 and 30 that is opposite from a surface facing the liquid crystal layer; and forming a second light blocking portion BL2 in the recess.
    Type: Application
    Filed: October 7, 2011
    Publication date: September 12, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Shigeki Tanaka, Nobufumi Tomimaru, Makoto Kanbe, Shunichi Takeuchi, Taimi Oketani
  • Publication number: 20120229736
    Abstract: Disclosed is a liquid crystal panel that can prevent a light leakage from the outside through a sealing portion and that can achieve excellent display quality and a narrower frame. The liquid crystal panel 10 is provided with, in a non-display region 10B on a surface of a first substrate 11 on a side facing a second substrate 12, a black matrix installation area 30, which includes a black matrix forming section 32 and a black matrix non-forming section 34 that is enclosed by the black matrix forming section. A sealing portion 16 is formed in the black matrix installation area 30 such that a portion thereof that makes direct contact with the first substrate 11 is arranged in the black matrix non-forming section 34.
    Type: Application
    Filed: October 7, 2010
    Publication date: September 13, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tomofumi Osaki, Taimi Oketani
  • Patent number: 6686322
    Abstract: A cleaning agent which comprises 0.1 to 60% by weight of an oxidizing agent and 0.0001 to 5% by weight of a chelating agent. In the process for producing semiconductor integrated circuits, a pattern layer of a photoresist used as an etching mask and residues formed from the photoresist by dry etching can be easily removed with the cleaning agent. In the process for producing substrates for liquid crystal display panels, residues derived from a conductive thin film formed by dry etching can also be easily removed. In the cleaning processes using the cleaning agent, wiring materials or insulating materials in thin film circuit devices or other materials used for producing substrates of semiconductor integrated circuits and liquid crystal panels are not corroded.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: February 3, 2004
    Assignees: Sharp Kabushiki Kaisha, Mitsubishi Gas Chemical Company, Inc.
    Inventors: Masahiro Nohara, Ryou Hashimoto, Taimi Oketani, Hisaki Abe, Taketo Maruyama, Tetsuo Aoyama
  • Patent number: 6617097
    Abstract: The present invention aims at reducing the number of scanning exposure and at enhancing throughput. the above-mentioned objective is achieved by allowing a substrate 14 to be placed in sideways with respect to a substrate holder 15a (placing the longer sides of the substrate in parallel to the shorter sides of the substrate holder) depending on the size of the apparatus and the size of the substrate 14. It is acceptable even when areas other than an effective exposure area of the substrate 14 should project out from the substrate holder.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: September 9, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasunori Nishimura, Taimi Oketani, Tsuyoshi Naraki
  • Patent number: 6523701
    Abstract: A cassette for supporting substrates and an elongated rib therefor is described and represents a further improvement in the previously proposed elongated rib systems of the prior art and is designed particularly to preclude deflection and dampen vibrations of loaded substrates. The elongated ribs for the cassette project from side panels utilizing an elongated rib structure including three segments; namely, a base resin body, a bar-like intermediate resin body extending from the base resin body, and a terminal resin body disposed at the forward end of the intermediate resin body. Preferably, the elongated rib structure includes a linearreinforcing member inserted fromthe base resin body to the intermediate resin body or, alternatively, from the base resin body through the intermediate resin body to the terminal resin body.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: February 25, 2003
    Assignees: Yodogawa Kasei Kabushiki Kaisha, Sharp Kabushiki Kaisha
    Inventors: Toshio Yoshida, Yuji Amano, Taimi Oketani, Masayuki Tsuji, Isao Saraoka
  • Patent number: 6500270
    Abstract: A resist film removing composition used in the manufacture of a thin film circuit element having an organic insulation film which comprises 50 to 70% by weight of an alkanolamine having 3 or more carbon atoms, 20 to 30% by weight of a water-miscible solvent and 10 to 20% by weight of water. The resist film removing composition can easily remove a resist film remaining after etching, without swelling the organic insulation film.
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: December 31, 2002
    Assignees: Sharp Corporation, Mitsubishi Gas Chemical Company, Inc.
    Inventors: Masahiro Nohara, Yukihiko Takeuchi, Taimi Oketani, Taketo Maruyama, Tetsuya Karita, Hisaki Abe, Tetsuo Aoyama
  • Patent number: 6496249
    Abstract: The present invention aims at preventing deterioration of flatness of a substrate and contamination of a substrate-holding surface of a substrate holder, which are caused by a resist leaking into the back surface of the substrate. A substrate-holding surface of a substrate holder is provided with a first pair of grooves 31 and 32 extending from one end to the other along a scanning direction and a second pair of grooves 33 and 34 extending from one end to the other along a direction generally perpendicular to the scanning direction. The first and second grooves are positioned such that they make contact with the periphery of the substrate when the substrate is vertically or horizontally placed on the substrate holder. Even when a resist on a substrate leaks into the periphery of the back surface, the resist escapes into the grooves, thereby preventing deterioration of the flatness of the substrate or contamination of the substrate-holding surface.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: December 17, 2002
    Assignees: Sharp Kabushiki Kaishi, Nikon Corporation
    Inventors: Yasunori Nishimura, Taimi Oketani, Tsuyoshi Naraki
  • Patent number: 6368756
    Abstract: A photomask of the present invention is a photomask for use in production of a display device, the photomask having on its surface a plurality of drawn areas and a transitional portion between two adjacent ones of the drawn areas. A pattern is formed on at least one of the drawn areas. A ratio between a pattern pitch and a transitional portion pitch is an integral ratio such that a length defined by a least common multiple of the pattern pitch and the transitional portion pitch is 1 mm or less.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: April 9, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shigeyuki Yamada, Taimi Oketani, Yoshinori Shimada