Abstract: A circuit includes a first plurality of memory cells coupled with a first data line and a first data transfer circuit coupled with the first data line and a second data line. In a first operation mode of the circuit, the first data line is left floating and is caused to have a first logical value by a current in at least one memory cell of the first plurality of memory cells. In a second operation mode of the circuit, the first data line is configured to reflect data stored in a memory cell of the plurality of memory cells, and the second data line is configured to reflect the data on the first data line through the first data transfer circuit.

Abstract: A chemical solution for use in cleaning a patterned substrate includes water, from approximate 0.01 to 99.98 percent by weight; hydrogen peroxide, from 0 to 30 percent by weight; a pH buffering agent, from approximate 0.01 to 50 percent by weight; a metal chelating agent, from approximate 0 to 10 percent by weight; and a compound for lowering a surface tension of the combination of water, hydrogen peroxide, pH buffering agent, and metal chelating agent. Examples of the compound include an organic solvent, from approximate 0 to 95 percent by weight, or a non-ionic surfactant agent, from approximate 0 to 2 percent by weight.

Abstract: Among other things, one or more techniques and systems for selectively filtering RF signals within one or more RF frequency band are provided. In particular, an RF choke, such as a 3D RF choke or a semi-lumped RF choke, configured to selectively filter such RF signals is provided. The RF choke comprises a metal connection line configured as an inductive element for the RF choke. In an example, one or more metal lines, such as a metal open stub, are formed as capacitive elements for the RF choke. In another example, one or more through vias are formed as capacitive elements for the RF choke. In this way, the RF choke allows DC power signals to pass through the metal connection line, while impeding RF signals within the one or more RF frequency bands from passing through the metal connection line.

Abstract: A method includes forming a passivation layer over a metal pad, wherein the metal pad is further overlying a semiconductor substrate of a wafer. A Post-Passivation Interconnect (PPI) is formed to electrically couple to the metal pad, wherein a portion of the PPI is overlying the passivation layer. A metal bump is formed over and electrically coupled to the PPI. The method further includes applying a molding compound over the metal bump and the PPI, applying a release film over the molding compound, pressing the release film against the molding compound, and curing the molding compound when the release film is pressed against the molding compound. The release film is then removed from the molding compound. The wafer is sawed into dies using a blade, with the blade cutting through the molding compound.

Abstract: An embodiment includes a substrate, wherein a portion of the substrate extends upwards forming a fin, a gate dielectric over a top surface and at least portions of sidewalls of the fin, a gate electrode over the gate dielectric, and a contact over and extending into the gate electrode, wherein the contact has a first width above the gate electrode and a second width within the gate electrode, the first width being smaller than the second width.

Abstract: An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.

Abstract: A method for forming a resistive memory cell within a memory array includes forming a patterned stopping layer on a first metal layer formed on a substrate and forming a bottom electrode into features of the patterned stopping layer. The method further includes forming a resistive memory layer. The resistive memory layer includes a metal oxide layer and a top electrode layer. The method further includes patterning the resistive memory layer so that the top electrode layer acts as a bit line within the memory array and a top electrode of the resistive memory cell.

Abstract: A method of fabricating a semiconductor device comprises forming a first dielectric material layer on a semiconductor substrate. The first dielectric material layer is patterned to form a plurality of vias therein. A metal layer is formed on the first dielectric material layer, wherein the metal layer fills the plurality of vias. The metal layer is etched such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal features aligned with the plurality of vias respectively. A self-assembled monolayer film is formed on surfaces of the plurality of metal features.

Abstract: Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired.

Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.

Abstract: A Fin-FET fabrication approach and structure are provided using channel epitaxial regrowth flow (CRF). The method includes forming a Fin-FET structure including a Si line on a substrate, shallow trench isolation (STI) oxide on both sides of the Si line on the substrate, and a poly wall on top of and across the STI oxide and the Si line, wherein the Si line is higher than the STI oxide from the substrate. The method further includes thinning the STI oxide and the Si line while maintaining about the same height ratio of the Si line and the STI oxide, and forming a spacer wall adjacent to both sides of the poly wall and further adjacent to Si and STI oxide side walls under the poly wall uncovered due thinning the STI oxide and the Si line.

Abstract: The present disclosure provides a biochip and methods of fabricating. The biochip includes a fluidic part and a sensing part bonded together using a polymer. The fluidic part has microfluidic channel pattern on one side and fluidic inlet and fluidic outlet on the other side that are fluidly connected to the microfluidic channel pattern. The fluidic inlet and fluidic outlet are formed by laser drilling after protecting the microfluidic channel pattern with a sacrificial protective layer. The polymer bonding is performed at low temperature without damaging patterned surface chemistry on a sensing surface of the sensing part.

Abstract: A semiconductor device comprises a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring. The device may comprise a passivation layer on the substrate, a polymer layer, a post-passivation interconnect (PPI) layer in contact with the bond pad, and a connector on the PPI layer, wherein the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring. The alignment mark may be at the PPI layer. There may be multiple alignment marks at different layers. There may be multiple alignment marks for the device around the corners or at the edges of an area surrounded by the guard ring.

Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.

Abstract: A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. An oxygen-rich layer is formed over the dielectric material layer. The dielectric material layer and the oxygen-rich layer are patterned to form a plurality of vias in the semiconductor substrate. A barrier layer is formed in the plurality of vias and on the dielectric material layer leaving a portion of the oxygen-rich layer exposed. A metal layer is formed on the barrier layer and on the exposed portion of the oxygen-rich layer, wherein the metal layer fills the plurality of vias. The semiconductor substrate is annealed at a predetermined temperature range and at a predetermined pressure to transform the exposed portion of the oxygen-rich layer into a metal-oxide stop layer.

Abstract: Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region. The packaging device includes a stress isolation structure (SIS) disposed on the packaging substrate proximate a portion of a perimeter of the semiconductor device mounting region.

Abstract: An integrated circuit structure includes a package component, which includes a dielectric layer and a metal trace over and in contact with the dielectric layer. The dielectric layer includes a first dielectric material and a second dielectric material in the first dielectric material. The first dielectric material is a flowable and curable material. The second dielectric material comprises a functional group selected from the group consisting essentially of (—C—N—), (—C—O—), (—N—C?O), and combinations thereof.

Abstract: The present disclosure provides one embodiment of a method of fabricating an integrated circuit. The method includes forming a patterned hard mask on a substrate; performing a fabrication process to the substrate through openings of the patterned hard mask; performing a first etch process to remove the patterned hard mask; and applying an NHD solution to the substrate, wherein the NHD solution includes ammonium hydroxide, hydrogen peroxide and deionized water with ratios tuned such that the NHD solution is weak basic.

Abstract: A semiconductor device structure and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method comprising forming a first conductive line over a substrate, and conformally forming a first dielectric layer over a top surface and a sidewall of the first conductive line, the first dielectric layer having a first porosity percentage and a first carbon concentration. The method further comprises forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a second porosity percentage and a second carbon concentration, the second porosity percentage being different from the first porosity percentage, and the second carbon concentration being less than the first carbon concentration.