Patents by Inventor Taizo Shirai

Taizo Shirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140247937
    Abstract: A processing unit transforms first input information into first nonlinear transformed information that is transformed into first linear transformed information, and transforms second input information into second nonlinear transformed information that is transformed into second linear transformed information. An exclusive-or section performs an exclusive-or operation based on the first and second linear transformed information. When the first nonlinear and linear transformed information are expressed as a first and second sequence vector, respectively, and the second nonlinear and linear transformed information are expressed as a third and fourth sequence vector, respectively, then a first row vector chosen from a first inverse matrix of a first matrix that transforms the first sequence vector to the second sequence vector, and a second row vector chosen from a second inverse matrix of a second matrix that transforms the third sequence vector to the fourth sequence vector, are linearly independent.
    Type: Application
    Filed: May 15, 2014
    Publication date: September 4, 2014
    Applicant: SONY CORPORATION
    Inventors: Taizo SHIRAI, Bart Preneel
  • Patent number: 8826025
    Abstract: Provided is an authentication device including a key setting unit for setting a multi-order polynomial ui(t) (i=1 to n?1) to a secret key and setting a multi-order polynomial f that satisfies f(u1(t), . . . , un-1(t),t)=0 to a public key, a message transmission unit for transmitting a message c to a verifier, a verification pattern reception unit for receiving information on one verification pattern selected by the verifier from k (k?3) verification patterns for one message c, and a response transmission unit for transmitting, to the verifier, response information, among k types of response information, corresponding to the information on the verification pattern received by the verification pattern reception unit. The response information is information that enables calculation of the secret key ui in a case all of the k verification patterns for the message c performed by using the k types of response information have been successful.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: September 2, 2014
    Assignee: Sony Corporation
    Inventors: Koichi Sakumoto, Taizo Shirai, Harunaga Hiwatari
  • Patent number: 8824671
    Abstract: A data conversion algorithm achieving efficient data diffusion is achieved. For example, in a configuration where a various processes are executed on two data segments which are resultants of dividing a rectangular matrix of data containing arranged one-byte data blocks into two parts to perform data conversion, efficient data scrambling with less operation cost is achieved by executing a linear conversion process on one of the data segments, an exclusive OR operation between the two data segments, a shift process on one of the data segments, and a swap process between the two data segments. Moreover, cryptographic processing with a high security level is achieved by including nonlinear conversion or key application operation on the data segments.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: September 2, 2014
    Assignee: Sony Corporation
    Inventors: Taizo Shirai, Kyoji Shibutani, Shiho Moriai, Toru Akishita, Tetsu Iwata
  • Publication number: 20140233729
    Abstract: There is provided a highly secure cryptographic processing apparatus and method where an analysis difficulty is increased. In a Feistel type common key block encrypting process in which an SPN type F function having a nonlinear conversion section and a linear conversion section is repeatedly executed a plurality of rounds. The linear conversion process of an F function corresponding to each of the plurality of rounds is performed as a linear conversion process which employs an MDS (Maximum Distance Separable) matrix, and a linear conversion process is carried out which employs a different MDS matrix at least at each of consecutive odd number rounds and consecutive even number rounds. This structure makes it possible to increase the minimum number (a robustness index against a differential attack in common key block encryption) of the active S box in the entire encrypting function.
    Type: Application
    Filed: December 30, 2013
    Publication date: August 21, 2014
    Inventors: Taizo SHIRAI, Kyoji SHIBUTANI
  • Publication number: 20140223193
    Abstract: A signature verification apparatus including a signature acquisition unit configured to acquire a digital signature including first information generated based on a pair of multi-order multivariate polynomials F=(f1, . . . , fm) defined in a ring K, a signature key s which is an element of a set Kn, and a document M and a plurality of pieces of second information for verifying that the first information is generated using the signature key s based on the data M, the pair of multi-order multivariate polynomials F, and vectors y=(f1(s), . . . , fm(s)), and a signature verification unit configured to verify legitimacy of the document M by confirming whether or not the first information is restorable using the plurality of pieces of second information included in the digital signature. The pair of multivariate polynomials F and the vectors y are public keys.
    Type: Application
    Filed: July 19, 2012
    Publication date: August 7, 2014
    Applicant: SONY CORPORATION
    Inventors: Koichi Sakumoto, Taizo Shirai, Harunaga Hiwatari
  • Publication number: 20140215222
    Abstract: Provided an information processing apparatus including a number generation unit configured to generate numbers used in coefficients of terms included in a pair of multi-order multivariate polynomials F=(f1, . . . , fm), using a predetermined function, from information shared between entities executing an algorithm of a public-key authentication scheme or a digital signature scheme that uses a public key including the pair of multi-order multivariate polynomials F, and an allocation unit configured to allocate the numbers generated by the number generation unit to the coefficients of the multi-order multivariate polynomials for which the pair of multi-order multivariate polynomials F are included in constituent elements.
    Type: Application
    Filed: August 14, 2012
    Publication date: July 31, 2014
    Applicant: SONY CORPORATION
    Inventors: Koichi Sakumoto, Taizo Shirai, Harunaga Hiwatari, Kazuya Kamio
  • Publication number: 20140211940
    Abstract: Provided is an information processing apparatus including a binary random number generation unit configured to generate a binary random number string expressed with binary numbers of M bits (where M?2), and a ternary number string generation unit configured to generate a ternary number string by grouping the binary random number string in units of k bits and generating binary number strings of the k bits and by expressing the binary number strings of the k bits with ternary numbers of L symbols (where L is a maximum integer satisfying 3L?2M). The ternary number string generation unit generates the ternary number string by expressing a binary number string X of the k bits satisfying X?3L with the ternary numbers of the L symbols.
    Type: Application
    Filed: July 19, 2012
    Publication date: July 31, 2014
    Applicant: SONY CORPORATION
    Inventors: Koichi Sakumoto, Taizo Shirai, Harunaga Hiwatari
  • Publication number: 20140208110
    Abstract: Provided is an information processing apparatus including a message generation unit configured to generate a message based on a pair of quadratic multivariate polynomials F=(f1, . . . , fm) defined in a ring K and expressed in a quadratic form and a vector s that is an element of a set Kn, a message supply unit configured to supply the message to a verifier storing the pair of quadratic multivariate polynomials F and vectors y=(y1, . . . , ym)=(f1(s), . . . , fm(s)), and a response supply unit configured to supply the verifier with response information corresponding to a verification pattern which the verifier selects from among k (where k?3) verification patterns.
    Type: Application
    Filed: July 20, 2012
    Publication date: July 24, 2014
    Applicant: SONY CORPORATION
    Inventors: Harunaga Hiwatari, Koichi Sakumoto, Taizo Shirai
  • Patent number: 8787563
    Abstract: A data converter for generating a hash value for message data is disclosed. The data converter executes a data conversion process, which includes compression-function execution sections and process sequences in which divided data blocks constituting message data are processed in parallel. Each compression-function execution section performs a process, using a message scheduling section and a chaining variable processing section. The message scheduling section receives a corresponding divided data block of the message data and performs a message scheduling process. The chaining variable processing section receives an output from the message scheduling section and an intermediate value output from a preceding processing section, and generates output data, which has the same number of bits as in the intermediate value. The compression-function execution sections may use one or more message scheduling sections and chaining variable processing sections.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: July 22, 2014
    Assignee: Sony Corporation
    Inventors: Taizo Shirai, Kyoji Shibutani, Shiho Moriai, Toru Akishita, Tetsu Iwata
  • Patent number: 8787568
    Abstract: A non-linear transformation processing structure having a high implementation efficiency and a high security is realized. Data transformation is performed using a first non-linear transformation part performing non-linear transformation using a plurality of small S-boxes; a linear transformation part receiving all the outputs from the first non-linear transformation part and performing data transformation using a matrix for performing optimal diffusion mappings; and a second non-linear transformation part including a plurality of small non-linear transformation parts that perform non-linear transformation on individual data units into which output data from the linear transformation part is divided. With this structure, appropriate data diffusion can be achieved without excessively increasing a critical path, and a structure with a high implementation efficiency and a high security can be achieved.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: July 22, 2014
    Assignee: Sony Corporation
    Inventors: Kyoji Shibutani, Taizo Shirai, Toru Akishita, Shiho Moriai
  • Publication number: 20140192973
    Abstract: A common-key blockcipher processing configuration with enhanced immunity against attacks such as saturation attacks and algebraic attacks (XSL attacks) is realized. In an encryption processing apparatus that performs common-key blockcipher processing, S-boxes serving as non-linear transformation processing parts set in round-function executing parts are configured using at least two different types of S-boxes. With this configuration, the immunity against saturation attacks can be enhanced. Also, types of S-boxes present a mixture of different types. With this configuration, the immunity against algebraic attacks (XSL attacks) can be enhanced, thereby realizing a highly secure encryption processing apparatus.
    Type: Application
    Filed: October 9, 2013
    Publication date: July 10, 2014
    Applicant: SONY CORPORATION
    Inventors: Taizo SHIRAI, Kyoji SHIBUTANI, Toru AKISHITA, Shiho MORIAI
  • Publication number: 20140192981
    Abstract: Provided is an information processing apparatus including a random number generation unit configured to generate a pair of random numbers from a seed, a message generation unit configured to generate a message based on a pair of multi-order multivariate polynomials F=(f1, . . . , fm) defined in a ring K, the pair of random numbers, and a vector s that is an element of a set Kn, a message supply unit configured to supply the message to a verifier storing the pair of multi-order multivariate polynomials F and vectors y=(y1, . . . , ym)=(f1(s), . . . , fm(s)), and a response supply unit configured to supply the verifier with response information corresponding to a verification pattern selected by the verifier from among k (where k?3) verification patterns.
    Type: Application
    Filed: August 17, 2012
    Publication date: July 10, 2014
    Applicant: SONY CORPORATION
    Inventors: Harunaga Hiwatari, Koichi Sakumoto, Taizo Shirai
  • Patent number: 8767956
    Abstract: A processing unit transforms first input information into first nonlinear transformed information that is transformed into first linear transformed information, and transforms second input information into second nonlinear transformed information that is transformed into second linear transformed information. An exclusive-or section performs an exclusive-or operation based on the first and second linear transformed information. When the first nonlinear and linear transformed information are expressed as a first and second sequence vector, respectively, and the second nonlinear and linear transformed information are expressed as a third and fourth sequence vector, respectively, then a first row vector chosen from a first inverse matrix of a first matrix that transforms the first sequence vector to the second sequence vector, and a second row vector chosen from a second inverse matrix of a second matrix that transforms the third sequence vector to the fourth sequence vector, are linearly independent.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: July 1, 2014
    Assignee: Sony Corporation
    Inventors: Taizo Shirai, Bart Preneel
  • Patent number: 8737603
    Abstract: To realize a common-key block cipher process configuration with increased difficulty of key analysis and improved security. In a configuration for storing in a register an intermediate key generated by using a secret key transformation process and performing a transformation process on the register-stored data to generate a round key, a process of swapping (permuting) data segments constituting the register-stored data is executed to generate a round key. For example, four data segments are produced so that two sets of data segments having an equal number of bits are set, and a process of swapping the individual data segments is repeatedly executed to generate a plurality of different round keys. With this configuration, the bit array of each round key can be effectively permuted, and round keys with low relevance can be generated. A high-security cryptographic process with increased difficulty of key analysis can be realized.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: May 27, 2014
    Assignee: Sony Corporation
    Inventors: Taizo Shirai, Kyoji Shibutani, Toru Akishita, Shiho Moriai
  • Patent number: 8731188
    Abstract: In extended Feistel type common key block cipher processing, a configuration is realized in which an encryption function and a decryption function are commonly used. In a cryptographic processing configuration to which an extended Feistel structure in which the number of data lines d is set to an integer satisfying d?3 is applied, involution properties, that is, the application of a common function to encryption processing and decryption processing, can be achieved. With a configuration in which round keys are permuted or F-functions are permuted in the decryption processing, processing using a common function can be performed by setting swap functions for the encryption processing and the decryption processing to have the same processing style.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: May 20, 2014
    Assignee: Sony Corporation
    Inventors: Kyoji Shibutani, Taizo Shirai, Toru Akishita, Shiho Moriai
  • Publication number: 20140122894
    Abstract: There is provided a print medium, whereon a public key used for authentication in a public-key authentication scheme is displayed as character information.
    Type: Application
    Filed: September 19, 2013
    Publication date: May 1, 2014
    Applicant: SONY CORPORATION
    Inventors: Koichi SAKUMOTO, Taizo Shirai, Harunaga Hiwatari
  • Publication number: 20140108798
    Abstract: There is provided an information processing device including a public key setter that sets a public key corresponding to a public-key authentication scheme in an access area defined as a given area of an object of access, and a device authentication processor that authenticates access to the access area against a secret key paired with the public key.
    Type: Application
    Filed: September 17, 2013
    Publication date: April 17, 2014
    Applicant: SONY CORPORATION
    Inventors: Taizo SHIRAI, Yu TANAKA
  • Patent number: 8675867
    Abstract: Provided is an information processing apparatus for realizing an electronic signature system of the MPKC signature method capable of safety certification with respect to chosen-message attack.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: March 18, 2014
    Assignee: Sony Corporation
    Inventors: Koichi Sakumoto, Taizo Shirai, Harunaga Hiwatari
  • Patent number: 8670558
    Abstract: To realize a common-key block cipher process configuration with increased difficulty of key analysis and improved security. In a configuration for storing in a register an intermediate key generated by using a secret key transformation process and performing a transformation process on the register-stored data to generate a round key, a process of swapping (permuting) data segments constituting the register-stored data is executed to generate a round key. For example, four data segments are produced so that two sets of data segments having an equal number of bits are set, and a process of swapping the individual data segments is repeatedly executed to generate a plurality of different round keys. With this configuration, the bit array of each round key can be effectively permuted, and round keys with low relevance can be generated. A high-security cryptographic process with increased difficulty of key analysis can be realized.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: March 11, 2014
    Assignee: Sony Corporation
    Inventors: Taizo Shirai, Kyoji Shibutani, Toru Akishita, Shiho Moriai
  • Patent number: 8666069
    Abstract: There is provided a highly secure cryptographic processing apparatus and method where an analysis difficulty is increased. In a Feistel type common key block encrypting process in which an SPN type F function having a nonlinear conversion section and a linear conversion section is repeatedly executed a plurality of rounds. The linear conversion process of an F function corresponding to each of the plurality of rounds is performed as a linear conversion process which employs an MDS (Maximum Distance Separable) matrix, and a linear conversion process is carried out which employs a different MDS matrix at least at each of consecutive odd number rounds and consecutive even number rounds. This structure makes it possible to increase the minimum number (a robustness index against a differential attack in common key block encryption) of the active S box in the entire encrypting function.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: March 4, 2014
    Assignee: Sony Corporation
    Inventors: Taizo Shirai, Kyoji Shibutani