Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits. good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.

Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.

Abstract: The present invention provides methods for inducing apoptosis in a cell, the methods generally involving contacting the cell with an agent that reduces the level and/or activity of RabGGT. The present invention further provides methods for treating a disorder related to unwanted cell proliferation in an individual, the methods generally involving administering to the individual an agent that reduces the level and/or activity of RabGGT. The present invention further provides methods for reducing apoptosis in a cell, the methods generally involving increasing the level and/or activity of RabGGT in the cell. The present invention further provides methods for treating disorders associated with excessive apoptosis. The present invention further provides methods for identifying a cell that is amenable to treatment with the methods of the present invention. The present invention further provides methods for modulating a binding event between RabGGT and a RabGGT interacting protein.

Abstract: A bipolar transistor structure and process technology is described incorporating a emitter, a base, and a collector, with most of the intrinsic base adjacent the collector having a graded energy bandgap and a layer of the intrinsic base adjacent the emitter having a substantially constant energy bandgap. The invention has a smaller base transit time than a conventional graded-base-bandgap bipolar transistor.

Abstract: A low programming power, high speed EEPROM device is disclosed which is adapted for large scale integration. The device comprises a body, a source, a drain, and it has means for injecting a programming current into the body. The hot carriers from the body enter the floating gate with much higher efficiency than channel current carriers are capable of doing. The drain current of this device is controlled by the body bias. The device is built on an insulator, with a bottom common plate, and a top side body. These features make the device ideal for SOI and thin film technologies.

Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.

Abstract: An IC including a resistor which is coupled to a metal wiring level through metal contacts, said resistor including a discrete metal-insulator-metal stack, wherein said metal contacts are in contact to one of said metals of said film stack. In the above IC design, current flows laterally through either the top metal electrode, the bottom metal electrode, or both, and any unused electrode is disconnected from the circuit.

Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.

Abstract: Human hPRP4 genes are identified as modulators of the p53 pathway, and thus are therapeutic targets for disorders associated with defective p53 function. Methods for identifying modulators of p53, comprising screening for agents that modulate the activity of hPRP4 are provided.

Abstract: Active devices that have either a thread or a ribbon geometry. The thread geometry includes single thread active devices and multiple thread devices. Single thread devices have a central core that may contain different materials depending upon whether the active device is responsive to electrical, light, mechanical, heat, or chemical energy. Single thread active devices include FETs, electro-optical devices, stress transducers, and the like. The active devices include a semiconductor body that for the single thread devices is a layer about the core of the thread. For the multiple thread devices, the semiconductor body is either a layer on one or more of the threads or an elongated body disposed between two of the threads. For example, a FET is formed of three threads, one of which carries a gate insulator layer and a semiconductor layer and the other two of which are electrically conductive and serve as the source and drain. The substrates or threads are preferably flexible and can be formed in a fabric.

Abstract: A bipolar transistor structure is described incorporating an emitter, base, and collector having a fully depleted region on an insulator of a Silicon-On-Insulator (SOI) substrate without the need for a highly doped subcollector to permit the fabrication of vertical bipolar transistors on semiconductor material having a thickness of 300 nm or less and to permit the fabrication of SOI BiCMOS. The invention overcomes the problem of requiring a thick semiconductor layer in SOI to fabricate vertical bipolar transistors with low collector resistance.

Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.

Abstract: An IC including a resistor which is coupled to a metal wiring level through metal contacts, said resistor including a discrete metal-insulator-metal stack, wherein said metal contacts are in contact to one of said metals of said film stack. In the above IC design, current flows laterally through either the top metal electrode, the bottom metal electrode, or both, and any unused electrode is disconnected from the circuit.

Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.

Abstract: An EEPROM device is described incorporating a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.

Abstract: An electrically erasable programmable read-only memory CEEPROM) includes a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.

Abstract: A process for fabricating Ultra Large Scale Integrated (ULSI) circuits in Silicon On Insulator (SOI) technology in which the device structures, which can be bipolar, FET, or a combination, are formed in vertical silicon sidewalls having insulation under and in back thereof so as to create SKI device structures. The silicon sidewall device SOI structures, when fabricated, take the form of cells with each cell having a plurality of either bipolar devices, FET devices, or a combination of these devices, such as collectors, emitters, bases, sources, drains, and gates interconnected within the planes of the regions of the devices in the cells and can be interconnected within the planes of the regions of devices in adjacent cells. Further, the interconnections to adjacent cells can be made from the back of the silicon sidewalls.

Abstract: Membranes suitable for use as wound dressings and in particular as synthetic skin substitutes are disclosed. The membranes consist of a natural or synthetic polymer, a non-gellable polysaccharide and a cross-linking agent.The membranes of the invention may contain one or more additional components selected from water-loss control agents, emulsifying agents and plasticizers. An internal reinforcing material may also be provided to supplement the inherent mechanical strength of the membrane.Methods of forming such membranes are also disclosed.

Abstract: The invention relates to a bipolar transistor structure which includes a layer of semiconductor material having a single crystal raised base, a single crystal or polycrystalline emitter and adjacent polycrystalline regions which provide an electrical connection to the emitter. The invention also relates to the method of fabricating such a structure and includes the step of depositing a conformal layer of semiconductor material of one conductivity type over a region of opposite conductivity and over insulation such that single crystal and polycrystalline regions form over single crystal material and insulation, respectively. In a subsequent step, a layer of opposite conductivity type semiconductor material is deposited on the first layer forming single crystal or polycrystalline material over single crystal and polycrystalline material over polycrystalline.

Abstract: A method consisting of a sequence of process steps for fabricating a bipolar transistor having base contacts formed of polysilicon material and an emitter contact formed of polysilicon material or metal. The emitter contact is self-aligned to the base contacts by the use of process steps wherein a single mask aperture is used for defining the base contacts and the emitter.