Abstract: Provided herein are methods of treating cancer using an effective amount of a compound represented by the formula (Formula (I)) or a pharmaceutically acceptable salt thereof and an effective amount of an immune checkpoint inhibitor. Also provided are compositions comprising the same compound represented by the formula shown above or a pharmaceutically acceptable salt thereof and an immune checkpoint inhibitor.

Abstract: Current tests for I/O interface connectors are described. In one example a test may include applying a forced energy to a first pin of an interface of a data communications bus of an integrated circuit on a die, sensing the energy caused by the forced energy at a second pin of the interface, and comparing the forced energy and the sensed energy to determine an amount of current leaked by at least a portion of the interface.

Abstract: I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing.

Abstract: Provided is an integrated circuit (IC) device having a support structure for use in a multi-dimensional (e.g., 3-D) die stack. The IC device includes a first chip (e.g., a memory die) positioned over a second chip (e.g., a logic layer), and a set of support structures between the memory die and the logic layer, wherein the set of support structures is arranged so as to radiate from a center of the memory die. In one approach, the set of support structures comprises two linear arrays each including a plurality of support members coupled to the memory die, the two linear arrays arranged in a standardized diagonal crossing configuration to provide increased stability between the memory die and the logic layer. In an exemplary embodiment, the set of support structures is connected to a power grid to help deliver power to circuitry of the memory die.

Abstract: Provided are a method and a system, in which a first device aligns a chip to a socket along a first axis. A second device aligns the chip to the socket along a second axis, and a third device aligns the chip to the socket along a plane formed by the first axis and a third axis. Also provided is a system comprising a first optical element, and a second optical element, where a first elastic element is coupled to the first optical element, and a second elastic element is coupled to the second optical element, and where the first elastic element is aligned to the second elastic element via elastic coupling.

Abstract: Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.

Abstract: I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing.

Abstract: Provided are a method and a system, in which a first device aligns a chip to a socket along a first axis. A second device aligns the chip to the socket along a second axis, and a third device aligns the chip to the socket along a plane formed by the first axis and a third axis. Also provided is a system comprising a first optical element, and a second optical element, where a first elastic element is coupled to the first optical element, and a second elastic element is coupled to the second optical element, and where the first elastic element is aligned to the second elastic element via elastic coupling.

Abstract: Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.

Abstract: Current tests for I/O interface connectors are described. In one example a test may include applying a forced energy to a first pin of an interface of a data communications bus of an integrated circuit on a die, sensing the energy caused by the forced energy at a second pin of the interface, and comparing the forced energy and the sensed energy to determine an amount of current leaked by at least a portion of the interface.

Abstract: In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a shadow pulse latch to generate at least one shadow latch signal in response to the data input signal and the pulsed system clock signal; and an output joining circuit, coupled to the system pulse latch and the shadow pulse latch, to provide a data output signal in response to the at least one system latch signal and the at least one shadow latch signal.

Abstract: In one embodiment, an apparatus includes a system circuit adapted to generate at a first output terminal a first output signal in response to a data input signal and at least one system clock signal; a shadow circuit adapted to generate at a second output terminal a second output signal in response the data input signal and the at least one system clock signal; and an output joining circuit coupled to at least the first output terminal and the second output terminal.

Abstract: In one embodiment, an apparatus is provided with a system circuit, a scanout circuit and an error detecting circuit. The system circuit is adapted to generate a first output signal in response to a data input signal and a system clock signal. The scanout circuit is adapted to generate a second output signal in response the data input signal and the system clock signal. The error detecting circuit, coupled to the system circuit and the scanout circuit, is adapted to generate an error signal in response to a relative condition between the first output signal and the second output signal.

Abstract: In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation; and an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.

Abstract: Methods, systems, and apparatuses are provided to emulate bus transactions for a device under test (DUT). Test data is sent from a testing device to a cache of a DUT. When data needs to be read or written to locations outside of the cache (e.g., bus action is needed), a pseudo bus agent (PBA) is activated. The PBA emulates the reads or writes and provides pseudo data back to the cache. In some embodiments, results of bus transactions are compressed to form a bus signature that is provided back to the testing device for validation.

Abstract: A method of testing a DUT is provided. The method comprises loading a memory within a link-based system with a functional test program, executing the functional test program in a processor core of the link-based system, and routing test signals generated during execution of the functional test program to a response agent embedded in the link-based system via an external path.

Abstract: A testing mode is provided for self testing of the transmitter and receiver pair provided on-chip. The testing mode targets each module individually; wherein when one of the two devices is placed under test, the other is used as a tester. When the transmitter is the device under test and the receiver is the tester that receives a transmitted signal from the transmitter, the receiver is used to determine the data eye size with the transmitted signal. When the receiver is the device under test and the transmitter is the tester, the transmitter is used to determine the amount of noise and power loss tolerated by the receiver.

Abstract: A method is provided. The method comprises loading a memory within a link-based system with a functional test program, executing the functional test program in a processor core of the link-based system, and routing test signals generated during execution of the functional test program to a response agent embedded in the link-based system via an external path.

Abstract: Methods, systems, and apparatuses are provided to emulate bus transactions for a device under test (DUT). Test data is sent from a testing device to a cache of a DUT. When data needs to be read or written to locations outside of the cache (e.g., bus action is needed), a pseudo bus agent (PBA) is activated. The PBA emulates the reads or writes and provides pseudo data back to the cache. In some embodiments, results of bus transactions are compressed to form a bus signature that is provided back to the testing device for validation.

Abstract: An apparatus and method for testing memory cells comprising coupling a first and a second memory cell to a first and a second bit lines, respectively, reading data from the first and second memory cells through the first and second bit lines, and comparing the voltage levels of the first and second bit lines.