Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.

Abstract: Bipolar junction transistor structures and methods for making the same are provide. The method includes: providing a substrate with an insulator layer and a device layer over the insulator layer, forming an intrinsic base from the device layer, forming emitter and collector regions from the device layer, and after forming i) the intrinsic base and ii) the emitter and collector regions, depositing a single crystalline extrinsic base over the intrinsic base.

Abstract: A stacked FinFET mask-programmable read only memory (ROM) is provided. The stacked FinFET mask-programmable ROM includes a fin structure extending upward from an insulator layer. In accordance with the present application, the fin structure includes, from bottom to top, a lower programmable semiconductor fin portion having a first threshold voltage, an insulator fin portion, and an upper programmable semiconductor fin portion having a second threshold voltage. A lower gate structure contacts a sidewall of the lower programmable semiconductor fin portion, and an upper gate structure contacts a sidewall of the upper programmable semiconductor fin portion.

Abstract: A vertical injection punchthrough based metal oxide semiconductor (VIPMOS) device and method of manufacturing the same, include a control gate, an erase gate, a floating gate, and an active area where the control gate, the erase gate, and the floating gate are coplanar and perpendicular to the active area.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.

Abstract: A shared floating gate device, the device including an nFET, a pFET including a different material than that of the nFET, and a floating gate.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.

Abstract: VFET-based mask-programmable ROM are provided. In one aspect, a method of forming a ROM device includes: forming a bottom drain on a wafer; forming fins on the bottom drain with a top portion having a channel dopant at a different concentration than a bottom portion of the fins; forming bottom/top dummy gates alongside the bottom/top portions of the fins; forming a source in between the bottom/top dummy gates; forming a top drain above the top dummy gates; removing the bottom/top dummy gates; and replacing the bottom/top dummy gates with bottom/top replacement gates, wherein the bottom drain, the bottom replacement gates, the bottom portion of the fins, and the source form bottom VFETs of the ROM device, and wherein the source, the top replacement gates, the top portion of the fins, and the top drain form top VFETs stacked on the bottom VFETs. A ROM device is also provided.

Abstract: A stacked FinFET mask-programmable read only memory (ROM) is provided. The stacked FinFET mask-programmable ROM includes a fin structure extending upward from an insulator layer. In accordance with the present application, the fin structure includes, from bottom to top, a lower programmable semiconductor fin portion having a first threshold voltage, an insulator fin portion, and an upper programmable semiconductor fin portion having a second threshold voltage. A lower gate structure contacts a sidewall of the lower programmable semiconductor fin portion, and an upper gate structure contacts a sidewall of the upper programmable semiconductor fin portion.

Abstract: A stacked FinFET programmable inverter is provided that includes a pFET gate structure including a floating gate and a thicker gate dielectric material layer than a gate dielectric material layer of an nFET gate structure stacked either above, or below, the nFET gate structure. In one embodiment, the pFET gate structure is below the nFET gate structure. In another embodiment, the pFET gate structure is above the nFET gate structure. The pFET gate structure contacts a sidewall of one semiconductor fin portion of a fin stack, while the nFET gate structure contacts a sidewall of another of the semiconductor fin portion of the same fin stack; the two semiconductor fin portions are separated by an insulator fin portion.

Abstract: An electrostatic discharge (ESD) protection structure containing a bottom diode and a top diode vertically stacked on the bottom diode is provided to render sufficient protection from ESD events with reduced diode footprint. The bottom diode is serially connected to the top diode via a conductive strap structure.

Abstract: A stacked FinFET programmable inverter is provided that includes a pFET gate structure including a floating gate and a thicker gate dielectric material layer than a gate dielectric material layer of an nFET gate structure stacked either above, or below, the nFET gate structure. In one embodiment, the pFET gate structure is below the nFET gate structure. In another embodiment, the pFET gate structure is above the nFET gate structure. The pFET gate structure contacts a sidewall of one semiconductor fin portion of a fin stack, while the nFET gate structure contacts a sidewall of another of the semiconductor fin portion of the same fin stack; the two semiconductor fin portions are separated by an insulator fin portion.

Abstract: Bipolar junction transistor structures and methods for making the same are provide. The method includes: providing a substrate with an insulator layer and a device layer over the insulator layer, forming an intrinsic base from the device layer, forming emitter and collector regions from the device layer, and after forming i) the intrinsic base and ii) the emitter and collector regions, depositing a single crystalline extrinsic base over the intrinsic base.

Abstract: VFET-based mask-programmable ROM are provided. In one aspect, a method of forming a ROM device includes: forming a bottom drain on a wafer; forming fins on the bottom drain with a top portion having a channel dopant at a different concentration than a bottom portion of the fins; forming bottom/top dummy gates alongside the bottom/top portions of the fins; forming a source in between the bottom/top dummy gates; forming a top drain above the top dummy gates; removing the bottom/top dummy gates; and replacing the bottom/top dummy gates with bottom/top replacement gates, wherein the bottom drain, the bottom replacement gates, the bottom portion of the fins, and the source form bottom VFETs of the ROM device, and wherein the source, the top replacement gates, the top portion of the fins, and the top drain form top VFETs stacked on the bottom VFETs. A ROM device is also provided.

Abstract: In one example, a sensor includes a heterojunction bipolar transistor and component sensing surface coupled to the heterojunction bipolar transistor via an extended base component. In another example, a biosensor for detecting a target analyte includes a heterojunction bipolar transistor and a sensing surface. The heterojunction bipolar transistor includes a semiconductor emitter including an emitter electrode for connecting to an emitter voltage, a semiconductor collector including a collector electrode for connecting to a collector voltage, and a semiconductor base positioned between the semiconductor emitter and the semiconductor collector. The sensing surface is coupled to the semiconductor base of the heterojunction bipolar transistor via an extended base component and includes a conducting film and a reference electrode.

Abstract: Bipolar junction transistor structures and methods for making the same are provide. The method includes: providing a substrate with an insulator layer and a device layer over the insulator layer, forming an intrinsic base from the device layer, forming emitter and collector regions from the device layer, and after forming i) the intrinsic base and ii) the emitter and collector regions, depositing a single crystalline extrinsic base over the intrinsic base.

Abstract: Bipolar junction transistor structures and methods for making the same are provide. The method includes: providing a substrate with an insulator layer and a device layer over the insulator layer, forming an intrinsic base from the device layer, forming emitter and collector regions from the device layer, and after forming i) the intrinsic base and ii) the emitter and collector regions, depositing a single crystalline extrinsic base over the intrinsic base.

Abstract: A shared floating gate device, the device including an. nFET, a pFET including a different material than that of the nFET, and a floating gate.

Abstract: A shared floating gate device, the device including an nFET, a pFET including a different material than that of the nFET, and a floating gate.