Patents by Inventor Takaaki Ukeda

Takaaki Ukeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6281562
    Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.
    Type: Grant
    Filed: July 24, 1996
    Date of Patent: August 28, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
  • Patent number: 6130139
    Abstract: The top surface of a P-type semiconductor substrate is partitioned into an active region to be formed with an element and an isolation region surrounding the active region. The isolation region is composed of trench portions and dummy semiconductor portions. An interlayer insulating film is deposited on the substrate, followed by a wire formed thereon. In each of the semiconductor portions, an impurity diffusion layer is formed simultaneously with the implantation of ions into the element so that a PN junction is formed between the impurity diffusion layer and the silicon substrate. A capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions is obtained by adding in series the capacitance in the impurity diffusion layer to the capacitance in the interlayer insulating film, which is smaller than the capacitance only in the inter layer insulating film.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: October 10, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takaaki Ukeda, Chiaki Kudo, Toshiki Yabu
  • Patent number: 6124160
    Abstract: A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled.
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: September 26, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mizuki Segawa, Toshiki Yabu, Takashi Uehara, Takashi Nakabayashi, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada
  • Patent number: 6069055
    Abstract: The fabricating method for semiconductor devices in which the trench technique is employed to perform isolation between devices, and which comprises the steps of sequentially depositing a first film 2, 3 and a second film 4 on top of a silicon substrate 1, forming an element isolation trench 5 in the silicon substrate 1 with masking of the first film 2, 3 and second film 4 which have undergone patterning, and growing a silicon oxide film 6 that is generated by reaction of ozone and tetra-ethyl-ortho-silicate inside the element isolation trench where silicon is exposed.
    Type: Grant
    Filed: July 1, 1997
    Date of Patent: May 30, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takaaki Ukeda, Toshiki Yabu, Takashi Uehara, Mizuki Segawa, Masatoshi Arai, Masaru Moriwaki
  • Patent number: 6034416
    Abstract: The top surface of a substrate in a peripheral circuit region is at a level that is higher than the top surface of the substrate in a memory cell region and that is substantially equal to the top surface of a floating gate electrode. A control gate electrode is formed on the floating gate electrode via a gate insulator film, and a gate electrode is formed on the substrate in the peripheral circuit region via a gate insulator film. The top surface of a buried insulator film for trench isolation may be at a level equal to the top surface of the floating gate electrode or to the top surface of an underlying film if the control gate electrode is formed of a multi-layer film. A level difference between the control gate electrode in the memory cell region and the gate electrode in the peripheral circuit region can be reduced, and thus fine patterns can be formed in these regions.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: March 7, 2000
    Assignee: Matsushita Electirc Industrial Co., Ltd.
    Inventors: Takashi Uehara, Toshiki Yabu, Mizuki Segawa, Takaaki Ukeda, Masatoshi Arai, Masaru Moriwaki
  • Patent number: 6008105
    Abstract: The semiconductor masking device of the invention includes a first semiconductor mask for forming an interconnection on a semiconductor substrate and a second semiconductor mask for forming a resist pattern on an insulating film. The first semiconductor mask has three masking areas and the second semiconductor mask has two masking areas. Masking area intervals, that is, the distances between the three masking areas of the first semiconductor mask and the two masking areas of the second semiconductor mask, are all equal to one another.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: December 28, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takaaki Ukeda, Tatsuya Yamada, Yoshiaki Kato, Akio Miyajima
  • Patent number: 5879983
    Abstract: A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled.
    Type: Grant
    Filed: September 18, 1996
    Date of Patent: March 9, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mizuki Segawa, Toshiki Yabu, Takashi Uehara, Takashi Nakabayashi, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada
  • Patent number: 5858578
    Abstract: The semiconductor masking device of the invention includes a first semiconductor mask for forming an interconnection on a semiconductor substrate and a second semiconductor mask for forming a resist pattern on an insulating film. The first semiconductor mask has three masking areas and the second semiconductor mask has two masking areas. Masking area intervals, that is, the distances between the three masking areas of the first semiconductor mask and the two masking areas of the second semiconductor mask, are all equal to one another.
    Type: Grant
    Filed: June 18, 1996
    Date of Patent: January 12, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takaaki Ukeda, Tatsuya Yamada, Yoshiaki Kato, Akio Miyajima