Patents by Inventor Takaaki Yamada

Takaaki Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040025023
    Abstract: A system for distributing broadcast contents, in which the copyright of the broadcast contents can be protected, is provided. The system is a watermarking application system for broadcast contents copyright protection, constituted by a broadcasting station of broadcast contents, a broadcasting receiver of the broadcast contents, a network monitoring agent for monitoring secondary contents of the broadcast contents, a secondary content player for playing secondary contents, communication receivers for recognizing distribution of secondary contents, etc. Pieces of digital watermarking embedding equipment are provided in the broadcasting station and the broadcasting receiver respectively. Pieces of digital watermarking extraction equipment are provided in the network monitoring agent and the secondary content player. Particularly, the broadcast contents are outputted through an analog output or an internal disk.
    Type: Application
    Filed: April 11, 2003
    Publication date: February 5, 2004
    Inventors: Takaaki Yamada, Hiroshi Yoshiura, Isao Echizen, Shuichi Tago, Seiichi Goshi, Kazuto Ogawa, Itsuro Murota, Go Otake
  • Patent number: 6650522
    Abstract: Because a semiconductor relay system of this invention comprises an across-element voltage detecting circuit 116 which delivers an across-element voltage detection signal depending on the presence/absence of an across-element voltage exceeding a predetermined threshold; an element driving circuit 112 for delivering an element driving signal in response to a control input signal; a logic-based judgement circuit 119 for delivering a logic-based judgement signal depending on the presence/absence of an across-element voltage detection signal; and a filtration circuit for removing a logic-based judgement signal of external disturbing elements to produce an element safety check signal, it is possible to reliably detect the disorder of a triac 114.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: November 18, 2003
    Assignee: Omron Corporation
    Inventors: Kenji Horibata, Teruyuki Nakayama, Toshiyuki Nakamura, Takaaki Yamada, Yuji Hashimoto, Kazuhiro Harada
  • Publication number: 20020060894
    Abstract: Because a semiconductor relay system of this invention comprises an across-element voltage detecting circuit 116 which delivers an across-element voltage detection signal depending on the presence/absence of an across-element voltage exceeding a predetermined threshold; an element driving circuit 112 for delivering an element driving signal in response to a control input signal; a logic-based judgement circuit 119 for delivering a logic-based judgement signal depending on the presence/absence of an across-element voltage detection signal; and a filtration circuit for removing a logic-based judgement signal of external disturbing elements to produce an element safety check signal, it is possible to reliably detect the disorder of a triac 114.
    Type: Application
    Filed: November 15, 2001
    Publication date: May 23, 2002
    Applicant: OMRON CORPORATION
    Inventors: Kenji Horibata, Teruyuki Nakayama, Toshiyuki Nakamura, Takaaki Yamada, Yuki Hashimoto, Kazuhiro Harada
  • Patent number: 6366909
    Abstract: An information presentation apparatus includes an information organization structure editing unit, a search condition creating unit, an information collection unit, and a collection result joining unit. The editing unit prompts a user to enter plural terms and one or more relations among said terms and store them as an information organization structure. The search condition creating unit creates a search condition of information from the terms and the relations among the terms stored in the information organization structure. The information collection unit searches information storage by using the created search condition and collect location information of the data meeting the search condition. The collection result joining unit visually joins the terms and the relations among the terms stored in the information organization structure with the location information of the searched data and displays the joined result.
    Type: Grant
    Filed: October 26, 1998
    Date of Patent: April 2, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Yuasa, Takaaki Yamada, Hiroyuki Kojima, Masato Tsuchibora
  • Patent number: 6208935
    Abstract: The present invention is directed to a map application system that employs an automatic stroll method of strolling through a virtual space into the route and distribution information change according to the interests of a user and the time of day (ie. daytime vs. nighttime, etc.). In the present invention, an article contributed to a contribution server from a contribution terminal is stored temporarily in a contribution DB. Each article is converted to information related to a spatial position by a spatial information structure process and is stored in a spatial information DB. The contribution server returns an article with the relation to the position of the neighborhood according to the input of a region name on a stroll terminal. The stroll terminal starts a stroll on the basis of a region name inputted as an initial value, and automatically sets a route on the basis of the interest information of a user. Information about the route is provided from contribution server and is appropriately displayed.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: March 27, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Takaaki Yamada, Shuji Kitazawa, Hiroshi Tsuji, Yoshiaki Yoshikawa, Maki Mori
  • Patent number: 6169469
    Abstract: A relay of the present invention comprises a coil plate 30 having at least one layer of spiral flat coil 36a-36d formed around each of a pair of holes 32, 33 and fixed contacts 23a, 24a and movable contacts which are opposed to each other contactably and separably via the holes 32, 33 in the coil plate 30. The fixed contacts 23a, 24a are provided on one side of each of a pair of flat core blocks 21, 22 juxtaposed and insulated from one another. The movable contacts are provided on one movable contactor 43 which is supported so as to be drivable along a direction of plate thickness via at least one hinge portion 42 extending from a support member 44 for a movable contact plate 40.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: January 2, 2001
    Assignee: Omron Corporation
    Inventors: Shuichi Misumi, Mitsuhiro Kawai, Takaaki Yamada
  • Patent number: 6084539
    Abstract: An analog signal, for example, a video signal is divided into a high frequency signal and a low frequency signal by a high-pass filter and a low-pass filter. A high speed analog-to-digital converter (ADC) converts the high frequency signal to a first digital code while a low speed but high precision ADC converts the low frequency signal to a second digital code. A synthesizer combines the first and second digital codes and outputs a digital code as the result of the conversion. Therefore, analog-to-digital conversion with a high speed, high precision, and high resolution can be realized.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: July 4, 2000
    Assignee: Sony Corporation
    Inventor: Takaaki Yamada
  • Patent number: 5726505
    Abstract: A device to prevent reverse current flow includes a diode connected between a power supply and a load. A switching device, connected in parallel with the diode, has a power loss that is smaller than that of the diode. A low-loss current detector, arranged to turn the switching device on and off, includes a DC current detector and a comparator. The comparator compares the detected DC current value with a threshold value for an operating current and generates an output signal that determines when the switching device should be turned on or off.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: March 10, 1998
    Assignee: Omron Corporation
    Inventors: Takaaki Yamada, Ikuo Nanno
  • Patent number: 5631648
    Abstract: A signal-processing circuit adapted for signal compression and expansion performed in the transmitter and receiver of mobile communication equipment. The signal-processing circuit comprises a multiplication type D/A converter to which an analog signal is applied, a level detector circuit that detects the level of the analog signal, and an A/D converter. The D/A converter converts the analog input signal into an analog output signal having an amplitude corresponding to digital control data. The A/D converter digitizes the output signal from the level detector circuit and supplies it as said digital control data to the D/A converter. These circuits can be fabricated from CMOS circuits.
    Type: Grant
    Filed: December 12, 1994
    Date of Patent: May 20, 1997
    Assignee: Sony Corporation
    Inventors: Takaaki Yamada, Kazuo Kumano, Kazuhiro Takeda
  • Patent number: 5623224
    Abstract: A communication circuit system of an IC card etc.
    Type: Grant
    Filed: August 24, 1995
    Date of Patent: April 22, 1997
    Assignee: Sony Corporation
    Inventors: Takaaki Yamada, Yasushi Nakamoto
  • Patent number: 5404168
    Abstract: A quantizing number is determined using multiple stages of code amount estimating circuits. Thus, an optimum quantizing number may be selected from among a number of quantizing numbers which is not limited to the number of code amount estimating circuits. The optimum quantizing number is used to quantize a set of blocks of orthogonally transformed image data. The quantized data are encoded using a variable length code. The optimum quantizing number is the one which results in the greatest amount of data that is within a predetermined threshold, permitting an amount of encoded data to be recorded on a magnetic tape in a fixed format.
    Type: Grant
    Filed: February 19, 1993
    Date of Patent: April 4, 1995
    Assignee: Sony Corporation
    Inventors: Takaaki Yamada, Naofumi Yanagihara, Hiroshi Okada
  • Patent number: 5347310
    Abstract: Apparatus for compression encoding video signals, comprising block segmenting circuits for segmenting a vertical interval, such as a field or frame, of video picture elements into a plurality of blocks of picture elements. An orthogonal transformation, such as discrete cosine transformation, of respective blocks is obtained, resulting in a two-dimensional array of transform coefficients of different values, the array being partitioned into respective areas. Each area is quantized with a respective quantizing value that differs for different areas. Preferably, a transform coefficient is quantized by dividing the value of the transform coefficients in an area by a divisor 2.sup.n/2, where n is an integer that differs in different areas. The areas of the two-dimensional array of transform coefficients are formed by partitioning the array in a direction substantially perpendicular to the oblique frequency axis of that array.
    Type: Grant
    Filed: December 16, 1992
    Date of Patent: September 13, 1994
    Assignee: Sony Corporation
    Inventors: Takaaki Yamada, Hiroshi Okada, Naofumi Yanagihara
  • Patent number: 5233316
    Abstract: A digital VCO is disclosed which comprises a ring oscillator formed of a plurality of inverters connected in series, each inverter being capable of controlling its delay amount, a frequency controlling circuit for controlling the oscillation frequency of the ring oscillator to coincide with a reference frequency, a selector switch for selecting specified output taps from output taps, each thereof being provided for each of the plurality of inverters, to take out the outputs therefrom, and switching control means for controlling the output taps from which the outputs are taken out to be cyclically switched through the selector switch.
    Type: Grant
    Filed: May 26, 1992
    Date of Patent: August 3, 1993
    Assignee: Sony Corporation
    Inventors: Takaaki Yamada, Hiroshi Yamagata
  • Patent number: 5211563
    Abstract: A computer assisted learning support system includes a storage for storing therein blocks of the teaching material respectively assigned with teaching material identifiers, the blocks being attained by subdividing the teaching material according to contents thereof, and link information which represents by a pair of identifiers of a teaching material a relationship between blocks of the teaching material, a display for presenting, in a change-over manner, a screen image of the blocks of the teaching material and a screen image of the contents of the blocks of the teaching material and the link information of the blocks, an input device for inputting therefrom a selection item for one of the displayed blocks of the teaching material items in response to the display thereof and a selection item for one of the link information items in response to the presentation of the contents of the blocks and the link information, a unit responsive to the selection for the block of the teaching material for displaying the c
    Type: Grant
    Filed: June 25, 1992
    Date of Patent: May 18, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Hirohide Haga, Hiroyuki Kojima, Takaaki Yamada
  • Patent number: 5057759
    Abstract: In a discrete-time alternating-current motor control apparatus having a state estimation observer estimating a rotor angle and a rotor angular velocity based on a direct quadrature transformation model of the motor, the gain of the observer is changed over depending on an estimated angular velocity. As a result, the apparatus is applicable in a wide range of the motor speed.Furthermore, the phase difference between the winding voltages and the winding currents supplied to the state estimation observer is compensated depending on the estimated angular velocity, thereby improving the control accuracy.
    Type: Grant
    Filed: June 27, 1990
    Date of Patent: October 15, 1991
    Assignee: Omron Corporation
    Inventors: Yoshihiro Ueda, Takaaki Yamada
  • Patent number: 5023615
    Abstract: In a digital-to-analog converter for converting a received digital signal having N bits and a sampling frequency fs to an analog signal; digital interpolation filter receives the digital signal and generates a modified digital signal having a number of bits less than N and a sampling frequency greater than fs, pulse width modulator receives the modified digital signal and generates a pulse signal having pulse widths which correspond to the modified digital signal, output buffer having a complementary metal oxide semiconductor (CMOS) inverter circuit including P channel and N channel transistors having respective resistance values receives the pulse signal and low-pass filter receives the output signal from the output buffer, wherein the digital interpolation filter, the pulse width modulator and the output buffer are formed in an integrated circuit, and when the transistors are conductive the resistance values of the P channel and N channel transistors are set equal to each other by adjusting a voltage applie
    Type: Grant
    Filed: February 20, 1990
    Date of Patent: June 11, 1991
    Assignee: Sony Corporation
    Inventors: Takaaki Yamada, Kazutoshi Shimizume
  • Patent number: 4592078
    Abstract: When the frequency dividing ratio of a programmable divider in a phase locked loop is controlled by an up/down counter, the designing of a system can be simplified by reducing the number of control lines connected to a microprocessor as much as possible. An up/down counter control circuit of the present invention comprises a timing control means to which a latch signal, a data and a clock signal are supplied, a data memory means and an up/down counter and is characterized in that under the control of the timing control means, in the data latch mode, a first level (0 or 1) of the latch signal is detected and in synchronism with the clock signal that data is latched in the data memory means, while in the up/down mode, a second level (1 or 0) of the latch signal is detected and the content of the up/down counter is changed in response to the level of the data synchronized with the clock signal.
    Type: Grant
    Filed: November 29, 1983
    Date of Patent: May 27, 1986
    Assignee: Sony Corporation
    Inventor: Takaaki Yamada
  • Patent number: 4533903
    Abstract: An analog-to-digital converter for converting an analog input voltage signal to a digital output voltage signal of m upper bits and n lower bits includes at least (2.sup.m+n -1) resistors connected in a series circuit to a voltage source for establishing respective reference voltages; at least (2.sup.m -1) upper bit voltage comparators for generating outputs indictive of the m upper bits, and having first and second inputs, the analog input voltage being applied to the first inputs and the second inputs being connected to the series circuit at respective intervals defining groups of the resistors; an upper bit encoder receiving the outputs of the upper bit voltage comparators and generating a switch control signal and a digital output voltage signal of m upper bits; at least (2.sup.
    Type: Grant
    Filed: July 8, 1982
    Date of Patent: August 6, 1985
    Assignee: Sony Corporation
    Inventors: Takaaki Yamada, Takeo Sekino
  • Patent number: 4521744
    Abstract: A tuning apparatus of phase-locked loop type having a voltage controlled oscillator which is working as a local oscillator of a tuning circuit, a programmable divider supplied with the output signal from the voltage controlled oscillator, a reference frequency signal generating circuit, a phase comparator supplied with the output signal from the voltage controlled oscillator and the output signal from the reference frequency signal generating circuit, and supplying the output signal to the voltage controlled oscillator, the programmable divider, the reference frequency signal generating circuit and the phase comparator being formed in a single integrated circuit, and a control circuit formed separately from the integrated circuit for supplying a control data to the programmable divider in the single integrated circuit is disclosed, in which the integrated circuit further comprises a memory for memorizing the control data which is serially supplied from the control circuit and supplying the control data to the
    Type: Grant
    Filed: December 17, 1982
    Date of Patent: June 4, 1985
    Assignee: Sony Corporation
    Inventors: Takaaki Yamada, Yukio Tsuda, Akira Yamakoshi
  • Patent number: 4490734
    Abstract: A variable impedance circuit employing an RIS field effect transistor which greatly reduces distortion at low and high frequencies is obtained by providing means for applying voltages to the RIS field effect transistor at values determined by the following equations: ##EQU1## where V.sub.BG is the backgate voltage, V.sub.D is the voltage applied to the drain, V.sub.S is the voltage applied to the source, V.sub.BO is the DC component of the voltage applied to the substrate, K is a constant, .alpha..sub.1 is a constant, .alpha..sub.2 is a constant, V.sub.GS is the voltage applied to the gate at the end nearest the source, V.sub.GD is voltage applied to the gate at the end nearest the drain and V.sub.GO is a control voltage.
    Type: Grant
    Filed: February 17, 1982
    Date of Patent: December 25, 1984
    Assignee: Sony Corporation
    Inventor: Takaaki Yamada