Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.

Abstract: A semiconductor device includes a first electrode, a second electrode, a third electrode, and a nitride semiconductor layer. The first electrode has a first surface. The second electrode has a second surface. The second surface is provided with a plurality of convex portions and concave portions. The second electrode is spaced from the first electrode in a first direction. The third electrode is spaced from the first electrode in a second direction intersecting the first direction. The nitride semiconductor layer is provided between the first surface and the second surface, and between the third electrode and the second surface.

Abstract: A semiconductor device includes a compound semiconductor layer, an insulating element, and a conductive element. The conductive element includes a plurality of conductive regions which are spaced from the compound semiconductor layer in a first direction. The insulating element is provided between the compound semiconductor layer and the conductive element. A length of each of the plurality of conductive regions in a second direction which intersects the first direction becomes longer the farther the individual one of the plurality of conductive regions is spaced from the compound semiconductor layer.

Abstract: According to one embodiment, a semiconductor device includes a GaN-based semiconductor layer, a resonator that uses a first portion of the GaN-based semiconductor layer as a piezoelectric layer to resonate, and a transistor that uses a second portion of the GaN-based semiconductor layer as a channel layer.

Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer including a first nitride semiconductor, a second semiconductor layer on the first semiconductor layer including a second nitride semiconductor, a source electrode, a drain electrode, a first gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode having a schottky junction, a second gate electrode provided above the second semiconductor layer intervening an insulating film, provided between the source electrode and the first gate electrode, electrically connected with the first gate electrode, and a third gate electrode provided above the second semiconductor layer intervening an insulating film, provided between the drain electrode and the first gate electrode, electrically connected with the first gate electrode.

Abstract: In one embodiment, a power supply circuit includes a first circuit including one or more first switching devices, and a first controller configured to control the first switching devices, the first circuit being configured to output a first voltage. The power supply circuit further includes a second circuit including one or more second switching devices which include a normally-on device, and a second controller configured to control the second switching devices, the second circuit being configured to output a second voltage generated from the first voltage. The second controller transmits a first signal for allowing the first circuit to output the first voltage, based on a value of a voltage or a current at a first node in the second circuit. The first controller allows the first circuit to output the first voltage by controlling the first switching devices in accordance with the first signal.

Abstract: In one embodiment, a semiconductor device includes a semiconductor chip including a nitride semiconductor layer, and including a control electrode, a first electrode and a second electrode provided on the nitride semiconductor layer. The device further includes a support including a substrate, and including a control terminal, a first terminal and a second terminal provided on the substrate. The semiconductor chip is provided on the support such that the control electrode, the first electrode and the second electrode face the support. The control electrode, the first electrode and the second electrode of the semiconductor chip are electrically connected to the control terminal, the first terminal and the second terminal of the support, respectively.

Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.

Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type. The device further includes a second semiconductor layer of the first conductivity type or the intrinsic type disposed above the first semiconductor layer. The device further includes a third semiconductor layer of a second conductivity type including a first upper portion in contact with the first semiconductor layer, a second upper portion located at a lower position than the first upper portion, a first side portion located between the first upper portion and the second upper portion, and a second side portion located at a lower position than the first side portion.

Abstract: This disclosure provides a semiconductor device which includes a GaN-based semiconductor layer having a surface with an angle of not less than 0 degree and not more than 5 degrees with respect to an m-plane or an a-plane, a first electrode provided above the surface and having a first end, and a second electrode provided above the surface to space apart from the first electrode, having a second end facing the first end, and a direction of a segment connecting an arbitrary point of the first end and an arbitrary point of the second end is different from a c-axis direction of the GaN-based semiconductor layer.

Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type. The device further includes a second semiconductor layer of the first conductivity type or the intrinsic type disposed above the first semiconductor layer. The device further includes a third semiconductor layer of a second conductivity type including a first upper portion in contact with the first semiconductor layer, a second upper portion located at a lower position than the first upper portion, a first side portion located between the first upper portion and the second upper portion, and a second side portion located at a lower position than the first side portion.

Abstract: According to one embodiment, a semiconductor device includes a SiC layer of a first conductivity type, a SiC region of a second conductivity type, and a conductive layer of the second conductivity type. The SiC layer of the first conductivity type has a hexagonal crystal structure. The SiC region of the second conductivity type is formed in a surface of the SiC layer. The conductive layer of the second conductivity type is provided on the SiC region and is in contact with a portion of the SiC region including SiC of a cubic crystal structure.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a semiconductor substrate, an insulating gate field-effect transistor, and a strain gauge unit. The semiconductor substrate is placed on the substrate and has first and second regions. The insulating gate field-effect transistor is provided in the first region of the semiconductor substrate. The strain gauge unit has a long metal resistor, a first insulating film and a second insulating film. The long metal resistor is provided inside of an upper surface of the semiconductor substrate in the second region of the semiconductor substrate. The first insulating film is provided between the semiconductor substrate and the metal resistor and extends up to the upper surface of the semiconductor substrate. The second insulating film is provided above the first insulating film across the metal resistor.

Abstract: According to one embodiment, a semiconductor device includes a SiC layer of a first conductivity type, a SiC region of a second conductivity type, and a conductive layer of the second conductivity type. The SiC layer of the first conductivity type has a hexagonal crystal structure. The SiC region of the second conductivity type is formed in a surface of the SiC layer. The conductive layer of the second conductivity type is provided on the SiC region and is in contact with a portion of the SiC region including SiC of a cubic crystal structure.

Abstract: According to one embodiment, a semiconductor device includes a SiC layer of a first conductivity type, a SiC region of a second conductivity type, and a conductive layer of the second conductivity type. The SiC layer of the first conductivity type has a hexagonal crystal structure. The SiC region of the second conductivity type is formed in a surface of the SiC layer. The conductive layer of the second conductivity type is provided on the SiC region and is in contact with a portion of the SiC region including SiC of a cubic crystal structure.

Abstract: According to one embodiment, a semiconductor device includes a SiC layer of a first conductivity type, a SiC region of a second conductivity type, and a conductive layer of the second conductivity type. The SiC layer of the first conductivity type has a hexagonal crystal structure. The SiC region of the second conductivity type is formed in a surface of the SiC layer. The conductive layer of the second conductivity type is provided on the SiC region and is in contact with a portion of the SiC region including SiC of a cubic crystal structure.

Abstract: A piezoelectric thin film device includes an amorphous metal film disposed on a substrate and a piezoelectric film disposed on the amorphous metal. One of crystal axis of the piezoelectric film is aligned in a direction perpendicular to a surface of the amorphous metal.

Abstract: A thin film piezoelectric resonator includes a substrate having a cavity; a first electrode extending over the cavity; a piezoelectric film placed on the first electrode; and a second electrode placed on the piezoelectric film, the second electrode having a periphery partially overlapping on the cavity and tapered to have an inner angle of 30 degrees or smaller defined by a part of the periphery thereof and a bottom thereof.

Abstract: A thin film piezoelectric actuator comprises a driving part at least one end of which is supported by an anchor portion. The driving part includes: a piezoelectric film, a first lower electrode provided under a first region of the piezoelectric film, a second lower electrode provided under a second region different from the first region of the piezoelectric film, a first upper electrode provided opposite to the first lower electrode on the piezoelectric film, a second upper electrode provided opposite to the second lower electrode on the piezoelectric film, a first connection part that electrically connects the first lower electrode and the second upper electrode via a first via hole formed in the piezoelectric film, and a second connection part that electrically connects the second lower electrode and the first upper electrode via a second via hole formed in the piezoelectric film.

Abstract: A piezoelectric device which is a MEMS device is provided. In the device, the entire silicon layer of the SOI substrate is a p-type region. A plurality of n-type regions are formed in the silicon layer so as to be exposed to the upper surface of the silicon layer and spaced from each other. A piezoelectric film made of AlN is provided on the SOI substrate so as to contact the n-type region, and a conductor film made of aluminum is provided on the piezoelectric film. Thereby, the n-type region functions as a lower electrode and the conductor film functions as an upper electrode.