Patents by Inventor Takafumi Hashiguchi

Takafumi Hashiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11592949
    Abstract: The touch panel built-in display includes a first electrode, a second electrode, and a third electrode for detecting the pressed state in which the protective plate is pressed. The first electrode is provided in the peripheral region on the back surface of the protective plate. The second and third electrodes are provided adjacent to each other in the peripheral region on the principal surface of the sensor substrate. That is, the first electrode, the second electrode, and the third electrode are provided in the peripheral region as a configuration for detecting the pressed state.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: February 28, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takafumi Hashiguchi, Tatsuya Nakamura, Yusuke Shimasaki, Takeshi Ono
  • Publication number: 20220045418
    Abstract: An object of the present disclosure is to suppress reduction of a communication distance of a touch screen with a built-in antenna and obtain a high visual quality at a time of constituting a display apparatus by the touch screen. A touch screen with a built-in antenna of the present disclosure is provided on a side of an emission of display light of a display element. The touch screen with the built-in antenna includes a touch panel and an antenna pattern. The antenna pattern includes an antenna wire disposed to overlap with a detectable area in a plan view and made by a repetitive unit pattern. A second pitch which is a pitch of the unit pattern of the antenna wire is different from a first pitch which is a pitch of the unit pattern of each of the first detection wires and each of the second detection wires.
    Type: Application
    Filed: May 28, 2021
    Publication date: February 10, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tatsuya NAKAMURA, Takafumi HASHIGUCHI, Seiichiro MORI
  • Patent number: 11126049
    Abstract: The display apparatus includes a plurality of gate lines, a plurality of vertical gate lines orthogonal to the gate lines, and a plurality of connection parts, each of which connects one of the gate lines and corresponding one of the vertical gate lines. The plurality of vertical gate lines extend from a first side in the display region. At least the gate line disposed closest to the first side is connected to the corresponding vertical gate line by a plurality of connection parts disposed at two or more locations.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: September 21, 2021
    Assignee: Trivale Technologies LLC
    Inventors: Tatsuya Baba, Takafumi Hashiguchi, Naruhito Hoka, Naoya Hirata
  • Publication number: 20210157456
    Abstract: The touch panel built-in display includes a first electrode, a second electrode, and a third electrode for detecting the pressed state in which the protective plate is pressed. The first electrode is provided in the peripheral region on the back surface of the protective plate. The second and third electrodes are provided adjacent to each other in the peripheral region on the principal surface of the sensor substrate. That is, the first electrode, the second electrode, and the third electrode are provided in the peripheral region as a configuration for detecting the pressed state.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 27, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takafumi HASHIGUCHI, Tatsuya NAKAMURA, Yusuke SHIMASAKI, Takeshi ONO
  • Patent number: 10852610
    Abstract: An opening insulation film covers a substrate and is in contact with a side surface of a gate electrode. The opening insulation film is provided with a first opening portion having a side surface on the gate electrode. A gate insulation film made of an oxide insulator is on the gate electrode and the opening insulation film. A semiconductor channel film made of an oxide semiconductor is on the gate insulation film and is encompassed by the first opening portion. Source and drain electrodes are on the semiconductor channel film. A source upper-layer electrode and a drain upper-layer electrode both made of an oxide are provided at least on upper surfaces of the source electrode and the drain electrode, respectively. An interlayer insulation film made of an oxide has a portion provided on the source upper-layer electrode and the drain upper-layer electrode and is in contact the semiconductor channel film.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: December 1, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazunori Inoue, Koji Oda, Takafumi Hashiguchi, Takeshi Kubota
  • Patent number: 10782579
    Abstract: First and second gate lines respectively extend in first and second directions in a display area. The second gate line is electrically connected to the first gate line and extends in the second direction in the display area. The second gate line is electrically connected to the first gate line outside the display area. A conductive layer may be disposed between the second gate line and a source line, and the second gate line may be electrically connected to the first gate line in the display area. To the conductive layer, a potential identical to a common potential or a ground potential is applied. An arrangement where two or more second gate lines overlap the source line may be employed. Transition of a potential of a gate signal from an on potential to an off potential may be made in two or more stages.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: September 22, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takafumi Hashiguchi, Naoya Hirata, Tatsuya Baba, Manabu Tanahara, Naruhito Hoka
  • Publication number: 20200174329
    Abstract: The display apparatus includes a plurality of gate lines, a plurality of vertical gate lines orthogonal to the gate lines, and a plurality of connection parts, each of which connects one of the gate lines and corresponding one of the vertical gate lines. The plurality of vertical gate lines extend from a first side in the display region. At least the gate line disposed closest to the first side is connected to the corresponding vertical gate line by a plurality of connection parts disposed at two or more locations.
    Type: Application
    Filed: November 26, 2019
    Publication date: June 4, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tatsuya BABA, Takafumi HASHIGUCHI, Naruhito HOKA, Naoya HIRATA
  • Patent number: 10622384
    Abstract: A liquid crystal display panel includes, on one of two substrates with liquid crystal held therebetween, first and second wires respectively arranged in a first and a second directions, third wires arranged in the first direction and connected to the second wires, pixels arranged corresponding to crossing positions between the first and the second wires, a first and a second driver ICs respectively connected to each first and each third wires. Each pixel includes a lower electrode, an upper electrode including slits, and domains alignment-divided in accordance with formation directions of the slits. One of the lower and the upper electrodes is a pixel electrode and the other is a common electrode. Each third wire is placed in a boundary between the domains. With this structure, provided is a liquid crystal display capable of narrowing a frame area and improving display quality.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: April 14, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tatsuya Baba, Takafumi Hashiguchi, Naoya Hirata
  • Publication number: 20190384132
    Abstract: First and second gate lines respectively extend in first and second directions in a display area. The second gate line is electrically connected to the first gate line and extends in the second direction in the display area. The second gate line is electrically connected to the first gate line outside the display area. A conductive layer may be disposed between the second gate line and a source line, and the second gate line may be electrically connected to the first gate line in the display area. To the conductive layer, a potential identical to a common potential or a ground potential is applied. An arrangement where two or more second gate lines overlap the source line may be employed. Transition of a potential of a gate signal from an on potential to an off potential may be made in two or more stages.
    Type: Application
    Filed: June 5, 2019
    Publication date: December 19, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takafumi HASHIGUCHI, Naoya HIRATA, Tatsuya BABA, Manabu TANAHARA, Naruhito HOKA
  • Publication number: 20190293980
    Abstract: An opening insulation film covers a substrate and is in contact with a side surface of a gate electrode. The opening insulation film is provided with a first opening portion having a side surface on the gate electrode. A gate insulation film made of an oxide insulator is on the gate electrode and the opening insulation film. A semiconductor channel film made of an oxide semiconductor is on the gate insulation film and is encompassed by the first opening portion. Source and drain electrodes are on the semiconductor channel film. A source upper-layer electrode and a drain upper-layer electrode both made of an oxide are provided at least on upper surfaces of the source electrode and the drain electrode, respectively. An interlayer insulation film made of an oxide has a portion provided on the source upper-layer electrode and the drain upper-layer electrode and is in contact the semiconductor channel film.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 26, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kazunori INOUE, Koji ODA, Takafumi HASHIGUCHI, Takeshi KUBOTA
  • Patent number: 10303298
    Abstract: A touch screen includes column-direction wirings extending in a column direction, row-direction wirings extending in a row direction orthogonal to the column direction, and detection cells provided in areas in which the column-direction wirings and the row-direction wirings are three-dimensionally intersect with each other. The touch screen further includes additional capacitors that are provided in a mounting region in which mounting terminals of a plurality of lead lines, each of which is connected to one of the column-direction wirings or one of the row-direction wirings, are mounted, and are configured to apply electrostatic capacitance to the plurality of lead lines, and at least one potential fixed terminal configured to fix a potential of one electrode of each of the additional capacitors.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: May 28, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takafumi Hashiguchi
  • Patent number: 10185196
    Abstract: Gate connection lines connected to gate wires in a display region are formed so as to have a region overlapped with source wires. According to such a structure, both of frame-width reduction and display performance of a liquid crystal display panel may be realized.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: January 22, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takafumi Hashiguchi, Naoya Hirata, Tatsuya Baba, Manabu Tanahara
  • Patent number: 10139688
    Abstract: In an FFS liquid crystal display in which a dummy pixel in a dummy pixel region is smaller than a display pixel in a display region, a slit is formed in a common electrode in the display pixel while no slit is formed in the common electrode in the dummy pixel.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: November 27, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takafumi Hashiguchi, Naruhito Hoka, Naoya Hirata
  • Publication number: 20180246386
    Abstract: Gate connection lines connected to gate wires in a display region are formed so as to have a region overlapped with source wires. According to such a structure, both of frame-width reduction and display performance of a liquid crystal display panel may be realized.
    Type: Application
    Filed: February 5, 2018
    Publication date: August 30, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takafumi HASHIGUCHI, Naoya HIRATA, Tatsuya BABA, Manabu TANAHARA
  • Publication number: 20180217431
    Abstract: A liquid crystal display panel includes, on one of two substrates with liquid crystal held therebetween, first and second wires respectively arranged in a first and a second directions, third wires arranged in the first direction and connected to the second wires, pixels arranged corresponding to crossing positions between the first and the second wires, a first and a second driver ICs respectively connected to each first and each third wires. Each pixel includes a lower electrode, an upper electrode including slits, and domains alignment-divided in accordance with formation directions of the slits. One of the lower and the upper electrodes is a pixel electrode and the other is a common electrode. Each third wire is placed in a boundary between the domains. With this structure, provided is a liquid crystal display capable of narrowing a frame area and improving display quality.
    Type: Application
    Filed: January 18, 2018
    Publication date: August 2, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tatsuya BABA, Takafumi HASHIGUCHI, Naoya HIRATA
  • Patent number: 9869915
    Abstract: An array substrate according to the present invention is an array substrate including a display region that displays an image and a frame region. The array substrate includes: a plurality of scanning lines; a plurality of signal lines; a thin film transistor disposed at an intersection of each of the plurality of scanning lines and each of the plurality of signal lines; a plurality of in-frame wires formed in the frame region; and a plurality of connection converters that electrically connect the scanning lines or the signal lines to the in-frame wires and are provided in the frame region. A single contact hole that penetrates an insulating layer is formed in each of the connection converters, and each of the scanning lines or each of the signal lines is electrically connected with each of the in-frame wires through a conductive film in the single contact hole.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: January 16, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takafumi Hashiguchi
  • Publication number: 20170351152
    Abstract: In an FFS liquid crystal display in which a dummy pixel in a dummy pixel region is smaller than a display pixel in a display region, a slit is formed in a common electrode in the display pixel while no slit is formed in the common electrode in the dummy pixel.
    Type: Application
    Filed: May 4, 2017
    Publication date: December 7, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takafumi HASHIGUCHI, Naruhito HOKA, Naoya HIRATA
  • Patent number: 9759969
    Abstract: A pixel electrode of an array substrate is connected with a drain electrode of a TFT via a first aperture formed on a second interlayer insulating film, a second aperture that includes a bottom portion of the first aperture and is formed on a common electrode, a third aperture that includes at least a part of the bottom portion of the first aperture, is included in a second aperture and is formed on a third interlayer insulating film, and a fourth aperture that is formed on the first interlayer insulating film in a region where the third aperture overlaps with the bottom portion of the first aperture.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: September 12, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masami Hayashi, Takafumi Hashiguchi
  • Patent number: 9690151
    Abstract: A liquid crystal panel includes an array substrate and a counter substrate facing the array substrate that are bonded to each other through a seal located along a peripheral edge. Vcom wiring and GND wiring are provided in a peripheral region of the array substrate. The Vcom wiring is provided between a display region and the GND wiring. The GND wiring extends beyond an edge of the seal.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: June 27, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takafumi Hashiguchi, Takeshi Shimamura, Naruhito Hoka, Hirofumi Iwanaga
  • Publication number: 20170131842
    Abstract: A touch screen includes column-direction wirings extending in a column direction, row-direction wirings extending in a row direction orthogonal to the column direction, and detection cells provided in areas in which the column-direction wirings and the row-direction wirings are three-dimensionally intersect with each other. The touch screen further includes additional capacitors that are provided in a mounting region in which mounting terminals of a plurality of lead lines, each of which is connected to one of the column-direction wirings or one of the row-direction wirings, are mounted, and are configured to apply electrostatic capacitance to the plurality of lead lines, and at least one potential fixed terminal configured to fix a potential of one electrode of each of the additional capacitors.
    Type: Application
    Filed: November 4, 2016
    Publication date: May 11, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventor: Takafumi HASHIGUCHI