Patents by Inventor Takafumi Hashiguchi

Takafumi Hashiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170068140
    Abstract: A pixel electrode of an array substrate is connected with a drain electrode of a TFT via a first aperture formed on a second interlayer insulating film, a second aperture that includes a bottom portion of the first aperture and is formed on a common electrode, a third aperture that includes at least a part of the bottom portion of the first aperture, is included in a second aperture and is formed on a third interlayer insulating film, and a fourth aperture that is formed on the first interlayer insulating film in a region where the third aperture overlaps with the bottom portion of the first aperture.
    Type: Application
    Filed: November 21, 2016
    Publication date: March 9, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Masami HAYASHI, Takafumi HASHIGUCHI
  • Patent number: 9553111
    Abstract: A pixel electrode of an array substrate is connected with a drain electrode of a TFT via a first aperture formed on a second interlayer insulating film, a second aperture that includes a bottom portion of the first aperture and is formed on a common electrode, a third aperture that includes at least a part of the bottom portion of the first aperture, is included in a second aperture and is formed on a third interlayer insulating film, and a fourth aperture that is formed on the first interlayer insulating film in a region where the third aperture overlaps with the bottom portion of the first aperture.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: January 24, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masami Hayashi, Takafumi Hashiguchi
  • Publication number: 20160103378
    Abstract: An array substrate according to the present invention is an array substrate including a display region that displays an image and a frame region. The array substrate includes: a plurality of scanning lines; a plurality of signal lines; a thin film transistor disposed at an intersection of each of the plurality of scanning lines and each of the plurality of signal lines; a plurality of in-frame wires formed in the frame region; and a plurality of connection converters that electrically connect the scanning lines or the signal lines to the in-frame wires and are provided in the frame region. A single contact hole that penetrates an insulating layer is formed in each of the connection converters, and each of the scanning lines or each of the signal lines is electrically connected with each of the in-frame wires through a conductive film in the single contact hole.
    Type: Application
    Filed: October 7, 2015
    Publication date: April 14, 2016
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Takafumi HASHIGUCHI
  • Patent number: 9257454
    Abstract: A pixel electrode is connected to a drain electrode of TFT via a first aperture formed on a second interlayer insulating film, a second aperture, which includes a bottom portion of the first aperture and is formed on a common electrode, and a third aperture, which is included in the bottom portion of the first aperture and is formed on a first interlayer insulating film and a third interlayer insulating film. The common electrode is connected to a common wiring via a fourth aperture formed on the second interlayer insulating film, and a fifth aperture that is included in a bottom portion of the fourth aperture and is formed on the first interlayer insulating film, and a contact electrode that is formed in the fourth aperture and the fifth aperture.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: February 9, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masami Hayashi, Takafumi Hashiguchi
  • Publication number: 20150241746
    Abstract: A liquid crystal panel includes an array substrate and a counter substrate facing the array substrate that are bonded to each other through a seal located along a peripheral edge. Vcom wiring and GND wiring are provided in a peripheral region of the array substrate. The Vcom wiring is provided between a display region and the GND wiring. The GND wiring extends beyond an edge of the seal.
    Type: Application
    Filed: February 11, 2015
    Publication date: August 27, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takafumi HASHIGUCHI, Takeshi SHIMAMURA, Naruhito HOKA, Hirofumi IWANAGA
  • Publication number: 20150076501
    Abstract: A pixel electrode of an array substrate is connected with a drain electrode of a TFT via a first aperture formed on a second interlayer insulating film, a second aperture that includes a bottom portion of the first aperture and is formed on a common electrode, a third aperture that includes at least a part of the bottom portion of the first aperture, is included in a second aperture and is formed on a third interlayer insulating film, and a fourth aperture that is formed on the first interlayer insulating film in a region where the third aperture overlaps with the bottom portion of the first aperture.
    Type: Application
    Filed: September 11, 2014
    Publication date: March 19, 2015
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masami HAYASHI, Takafumi HASHIGUCHI
  • Publication number: 20150034955
    Abstract: A pixel electrode is connected to a drain electrode of TFT via a first aperture formed on a second interlayer insulating film, a second aperture, which includes a bottom portion of the first aperture and is formed on a common electrode, and a third aperture, which is included in the bottom portion of the first aperture and is formed on a first interlayer insulating film and a third interlayer insulating film. The common electrode is connected to a common wiring via a fourth aperture formed on the second interlayer insulating film, and a fifth aperture that is included in a bottom portion of the fourth aperture and is formed on the first interlayer insulating film, and a contact electrode that is formed in the fourth aperture and the fifth aperture.
    Type: Application
    Filed: July 25, 2014
    Publication date: February 5, 2015
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masami HAYASHI, Takafumi HASHIGUCHI
  • Publication number: 20130334534
    Abstract: A liquid crystal display which includes a first substrate having thin film transistors, and a second substrate disposed to face the first substrate, wherein the first substrate includes: a gate electrode, a source electrode, and a drain electrode; a gate wiring; a first insulating film formed on the gate electrode and the gate wiring; a source wiring; a pixel electrode that is formed on the drain electrode to partially overlap the drain electrode; a second insulating film that covers the pixel electrode; a counter electrode; and a side wall that is formed on side portions of the source wiring, the source electrode, and the drain electrode, the third insulating film made of third insulating film; and wherein at least a part of the pixel electrode is formed to directly overlap the drain electrode and the side wall formed on the side portion of the drain electrode.
    Type: Application
    Filed: June 18, 2013
    Publication date: December 19, 2013
    Inventors: Tatsuya FUJII, Toru TAKEGUCHI, Takafumi HASHIGUCHI
  • Patent number: 7630049
    Abstract: A display device having a substrate provided with a display region includes a lower layer film formed on the substrate, a transparent conductive thin film formed on the lower layer film and electrically connected thereto, and a protective film formed on the transparent conductive film in a region other than the display region to prevent malformation of the transparent conductive thin film and the lower layer film.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: December 8, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takafumi Hashiguchi, Akio Nakayama, Yasushi Matsui
  • Patent number: 7599039
    Abstract: A mounting terminal substrate includes a substrate, mounting terminals arranged in staggered rows on the substrate, each mounting terminals includes a lower conductive film and an upper conductive film, lines that are provided between the mounting terminals in a direction of a row, an insulation film that covers the lines, and opening sections on the respective mounting terminals from which the insulation films are removed, wherein a width of the upper conductive film in the direction of the row is greater than a width of the lower conductive film in the direction of the row so as to cover the lower conductive films exposed through the opening sections and is equal to or smaller than a width of the opening section in the direction of the row.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: October 6, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shohei Yasuda, Takafumi Hashiguchi, Seiya Ueda
  • Publication number: 20090026462
    Abstract: A wiring substrate includes a plurality of lines provided on the substrate, and a plurality of mounting terminals each for respective one of the plurality of lines, the plurality of mounting terminals being arranged in several rows in a staggered pattern, wherein the mounting terminal includes a first conductive film formed in the same layer as the lines, an insulating film covering the lines and the first conductive film, the insulating film having an opening above the first conductive film, and an upper layer conducive film electrically connected to the first conductive film through the opening, and wherein the insulating film includes a thick film portion located on the outside of the area where the plurality of mounting terminals are arranged in several rows in the staggered pattern, and a thin film portion located in the area adjacent to the opening in the row direction of the staggered pattern with a thickness thinner than the thick film portion.
    Type: Application
    Filed: July 10, 2008
    Publication date: January 29, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Takafumi HASHIGUCHI
  • Publication number: 20080180627
    Abstract: A mounting terminal substrate includes a substrate, mounting terminals arranged in staggered rows on the substrate, each mounting terminals includes a lower conductive film and an upper conductive film, lines that are provided between the mounting terminals in a direction of a row, an insulation film that covers the lines, and opening sections on the respective mounting terminals from which the insulation films are removed, wherein a width of the upper conductive film in the direction of the row is greater than a width of the lower conductive film in the direction of the row so as to cover the lower conductive films exposed through the opening sections and is equal to or smaller than a width of the opening section in the direction of the row.
    Type: Application
    Filed: July 20, 2007
    Publication date: July 31, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shohei Yasuda, Takafumi Hashiguchi, Seiya Ueda
  • Patent number: 7405783
    Abstract: A display apparatus according to the present invention is provided with a gate line 2 formed on an insulating substrate, a source line 13 intersecting with the gate line 2 with an insulating film in between, a source electrode 6 connected to the source line 13, a drain electrode 10 connected to a pixel electrode 9, a semiconductor layer 4 formed below the source electrode 6, the source line 13, and the drain electrode 10, a light-shielding pattern 12 configured below the semiconductor layer 4 lying below the source line 13, and a backlight emitting lights from a light source to the surface of the insulating substrate opposite to where pixels are formed. In this configuration, leakage current arisen in the semiconductor layer lying below the source line, the extending pattern of the drain electrode, and so on can be suppressed.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: July 29, 2008
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hironori Aoki, Shigeaki Noumi, Takafumi Hashiguchi
  • Publication number: 20070097282
    Abstract: A thin film multilayer substrate includes a planarizing film having bumpy pattern on its surface, a plurality of first conductive parts below the planarizing film, and a second conductive parts above the planarizing film. The bumpy pattern on the surface of the planarizing film is formed in regions where salient parts of the first conductive parts are formed excluding regions the second conductive parts formed therein.
    Type: Application
    Filed: September 28, 2006
    Publication date: May 3, 2007
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takafumi Hashiguchi, Shinji Kawabuchi
  • Patent number: 7098969
    Abstract: The widths of those portions of a semiconductor layer 5 and a drain line 6a overlapping with it which cross an edge line of a gate electrode 2 are made smaller than the channel width of a thin-film transistor. With this measure, the overlap area of the gate electrode 2 and a drain electrode 6 is reduced. As a result, a variation of the above overlap area due to alignment errors in a photolithography apparatus used in patterning the gate lines 2, the drain electrodes 6, and source electrodes 7 can be reduced and the frequency of occurrence of display defects can be decreased.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: August 29, 2006
    Assignee: Kabushiki Kaisha Advanced Display
    Inventors: Takafumi Hashiguchi, Takehisa Yamaguchi, Naoki Nakagawa
  • Publication number: 20050231670
    Abstract: A display device having a substrate provided with a display region includes a lower layer film formed on the substrate, a transparent conductive thin film formed on the lower layer film and electrically connected thereto, and a protective film formed on the transparent conductive film in a region other than the display region to prevent malformation of the transparent conductive thin film and the lower layer film.
    Type: Application
    Filed: April 15, 2005
    Publication date: October 20, 2005
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Takafumi Hashiguchi, Akio Nakayama, Yasushi Matsui
  • Publication number: 20050230719
    Abstract: A display apparatus according to the present invention is provided with a gate line 2 formed on an insulating substrate, a source line 13 intersecting with the gate line 2 with an insulating film in between, a source electrode 6 connected to the source line 13, a drain electrode 10 connected to a pixel electrode 9, a semiconductor layer 4 formed below the source electrode 6, the source line 13, and the drain electrode 10, a light-shielding pattern 12 configured below the semiconductor layer 4 lying below the source line 13, and a backlight emitting lights from a light source to the surface of the insulating substrate opposite to where pixels are formed. In this configuration, leakage current arisen in the semiconductor layer lying below the source line, the extending pattern of the drain electrode, and so on can be suppressed.
    Type: Application
    Filed: June 7, 2005
    Publication date: October 20, 2005
    Applicant: ADVANCED DISPLAY INC.
    Inventors: Hironori Aoki, Shigeaki Noumi, Takafumi Hashiguchi
  • Patent number: 6919942
    Abstract: A display apparatus according to the present invention is provided with a gate line 2 formed on an insulating substrate, a source line 13 intersecting with the gate line 2 with an insulating film in between, a source electrode 6 connected to the source line 13, a drain electrode 10 connected to a pixel electrode 9, a semiconductor layer 4 formed below the source electrode 6, the source line 13, and the drain electrode 10, a light-shielding pattern 12 configured below the semiconductor layer 4 lying below the source line 13, and a backlight emitting lights from a light source to the surface of the insulating substrate opposite to where pixels are formed. In this configuration, leakage current arisen in the semiconductor layer lying below the source line, the extending pattern of the drain electrode, and so on can be suppressed.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: July 19, 2005
    Assignee: Advanced Display Inc.
    Inventors: Hironori Aoki, Shigeaki Noumi, Takafumi Hashiguchi
  • Publication number: 20050088599
    Abstract: The widths of those portions of a semiconductor layer 5 and a drain line 6a overlapping with it which cross an edge line of a gate electrode 2 are made smaller than the channel width of a thin-film transistor. With this measure, the overlap area of the gate electrode 2 and a drain electrode 6 is reduced. As a result, a variation of the above overlap area due to alignment errors in a photolithography apparatus used in patterning the gate lines 2, the drain electrodes 6, and source electrodes 7 can be reduced and the frequency of occurrence of display defects can be decreased.
    Type: Application
    Filed: November 16, 2004
    Publication date: April 28, 2005
    Applicant: KABUSHIKI KAISHA ADVANCED DISPLAY
    Inventors: Takafumi Hashiguchi, Takehisa Yamaguchi, Naoki Nakagawa
  • Patent number: 6882377
    Abstract: The liquid crystal display of the present invention includes: a first insulating substrate as an array substrate; display pixels formed in such a manner as to be arranged in array like shape on the first insulating substrate, said display pixels having pixel electrodes electrically connected to each other; a counter substrate formed on a second insulating substrate on which common electrodes are formed; a liquid crystal layer interposed between the first insulating substrate and the second insulating substrate, the first insulating substrate and the second insulating substrate being bonded each other; a transfer electrode for supplying a common electrical potential to common electrodes on the second insulating substrate through a conductive material; wherein the transfer electrode is formed by patterning a conductive thin film that has been formed by the last conductive film forming process of the first insulating substrate; wherein a second conductive metal film, which has been formed in the second conductiv
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: April 19, 2005
    Assignee: Advanced Display Inc.
    Inventors: Satoshi Kohtaka, Takafumi Hashiguchi, Yukio Endo