Patents by Inventor Takafumi Takatsuka
Takafumi Takatsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150138414Abstract: A solid-state imaging device includes a pixel array section that has at least one pixel with a photoelectric conversion unit and a charge detection unit. A driving section is configured to read out a signal of the pixel, a first portion of said signal being based on signal charge, a second portion of said signal being based on a reset potential. A signal processing section is configured to read out the first portion of the signal as a reference voltage, with the reference voltage being adjusted to cause the first and second portions of the signal to be within an input voltage range.Type: ApplicationFiled: January 30, 2015Publication date: May 21, 2015Inventors: Masaki Sakakibara, Tadayuki Taura, Yusuke Oike, Takafumi Takatsuka, Akihiko Kato
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Patent number: 8964086Abstract: A solid-state imaging device includes a pixel array section that has at least one pixel with a photoelectric conversion unit and a charge detection unit. A driving section is configured to read out a signal of the pixel, a first portion of said signal being based on signal charge, a second portion of said signal being based on a reset potential. A signal processing section is configured to read out the first portion of the signal as a reference voltage, with the reference voltage being adjusted to cause the first and second portions of the signal to be within an input voltage range.Type: GrantFiled: October 4, 2013Date of Patent: February 24, 2015Assignee: Sony CorporationInventors: Masaki Sakakibara, Tadayuki Taura, Yusuke Oike, Takafumi Takatsuka, Akihiko Kato
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Publication number: 20140368714Abstract: A solid-state imaging device includes a first chip including a plurality of pixels, each pixel including a light sensing unit generating a signal charge responsive to an amount of received light, and a plurality of MOS transistors reading the signal charge generated by the light sensing unit and outputting the read signal charge as a pixel signal, a second chip including a plurality of pixel drive circuits supplying desired drive pulses to pixels, the second chip being laminated beneath the first chip in a manner such that the pixel drive circuits are arranged beneath the pixels formed in the first chip to drive the pixels, and a connection unit for electrically connecting the pixels to the pixel drive circuits arranged beneath the pixels.Type: ApplicationFiled: September 2, 2014Publication date: December 18, 2014Inventors: Katsumi Honda, Takafumi Takatsuka
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Patent number: 8854517Abstract: A solid-state imaging device includes a first chip including a plurality of pixels, each pixel including a light sensing unit generating a signal charge responsive to an amount of received light, and a plurality of MOS transistors reading the signal charge generated by the light sensing unit and outputting the read signal charge as a pixel signal, a second chip including a plurality of pixel drive circuits supplying desired drive pulses to pixels, the second chip being laminated beneath the first chip in a manner such that the pixel drive circuits are arranged beneath the pixels formed in the first chip to drive the pixels, and a connection unit for electrically connecting the pixels to the pixel drive circuits arranged beneath the pixels.Type: GrantFiled: March 17, 2010Date of Patent: October 7, 2014Assignee: Sony CorporationInventors: Katsumi Honda, Takafumi Takatsuka
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Publication number: 20140049675Abstract: There is provided a solid-state imaging device including a pixel array section having a plurality of unit pixels two-dimensionally arranged therein, the unit pixels including at least a photoelectric conversion section, a charge holding section, a transfer section, and a reset section, and a drive control section which controls driving of the unit pixels in a manner that a voltage as a signal level and a voltage as a reset level are each read out serially per row. The drive control section controls readout of the voltage of the charge holding section in accordance with initialization of the charge holding section performed by the reset section before the charge transfer by the transfer section.Type: ApplicationFiled: July 30, 2013Publication date: February 20, 2014Applicant: SONY CORPORATIONInventors: Takafumi Takatsuka, Yusuke Oike, Masaki Sakakibara
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Publication number: 20140036123Abstract: A solid-state imaging device includes a pixel array section that has at least one pixel with a photoelectric conversion unit and a charge detection unit. A driving section is configured to read out a signal of the pixel, a first portion of said signal being based on signal charge, a second portion of said signal being based on a reset potential. A signal processing section is configured to read out the first portion of the signal as a reference voltage, with the reference voltage being adjusted to cause the first and second portions of the signal to be within an input voltage range.Type: ApplicationFiled: October 4, 2013Publication date: February 6, 2014Applicant: SONY CORPORATIONInventors: Masaki Sakakibara, Tadayuki Taura, Yusuke Oike, Takafumi Takatsuka, Akihiko Kato
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Patent number: 8576317Abstract: Disclosed herein is a solid-state image pickup apparatus, including a pixel array section in which a unit pixel including a photoelectric conversion section and a charge detection section for detecting charge generated by photoelectric conversion by the photoelectric conversion section is disposed; a driving section adapted to carry out driving of reading out a signal of the unit pixel divisionally by twice as a first signal and a second signal; and a signal processing section adapted to set the first signal read out first from the unit pixel as a reference voltage for a processable input voltage range of the signal processing section, adjust the reference voltage so that the first and second signals may be included in the input voltage range and carry out signal processing for the first and second signals using the adjusted reference voltage.Type: GrantFiled: March 21, 2011Date of Patent: November 5, 2013Assignee: Sony CorporationInventors: Masaki Sakakibara, Tadayuki Taura, Yusuke Oike, Takafumi Takatsuka, Akihiko Kato
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Patent number: 8493489Abstract: Disclosed herein is a solid-state imaging device, including: a pixel array unit configured to be formed by two-dimensionally arranging unit pixels each having a photoelectric converter, a charge-voltage converter, a reset transistor to set the charge-voltage converter to a predetermined potential, and an amplification transistor to read out a signal converted by the charge-voltage converter; a signal processor configured to process a signal output from the unit pixel by using a reference voltage; and a setter configured to set a reset level obtained from a second unit pixel from which a signal level has been already read out as the reference voltage of the signal processor before readout of a signal level based on a signal charge accumulated or retained in the charge-voltage converter from a first unit pixel.Type: GrantFiled: March 21, 2011Date of Patent: July 23, 2013Assignee: Sony CorporationInventors: Yusuke Oike, Akihiko Kato, Takafumi Takatsuka, Masaki Sakakibara
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Patent number: 8482645Abstract: Disclosed herein is a solid-state imaging device employing a plurality of unit pixels each having an opto-electric conversion section configured to convert incident light into electric charge and an electric-charge holding section configured to hold a signal voltage representing the electric charge produced by the opto-electric conversion section, the solid-state imaging device further including a read section and a control section.Type: GrantFiled: March 22, 2011Date of Patent: July 9, 2013Assignee: Sony CorporationInventors: Takafumi Takatsuka, Akihiko Kato, Yusuke Oike, Masaki Sakakibara
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Publication number: 20120154656Abstract: A solid-state imaging element is disclosed which includes: a pixel array portion configured to have a plurality of unit pixels arrayed two-dimensionally, the unit pixels being furnished with a photoelectric conversion portion, a transfer section, and a reset section, the transfer section being configured to transfer electrical charges accumulated in the photoelectric conversion portion to a charge retention portion, the reset section being configured to reset the electrical charges of the charge retention portion; and a drive control section configured to control the driving of the unit pixels; wherein the drive control section controls the driving of the unit pixels in such a manner that prior to the charge transfer by the transfer section, the reset section resets the electrical charges of the charge retention portion in increments of a plurality of rows of the unit pixels, the plurality of rows being not adjacent to one another.Type: ApplicationFiled: December 6, 2011Publication date: June 21, 2012Applicant: SONY CORPORATIONInventors: Yusuke OIKE, Takafumi TAKATSUKA, Ikuhiro YAMAMURA
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Publication number: 20120026370Abstract: Disclosed herein is a solid-state imaging device, including: a pixel array unit configured to be formed by two-dimensionally arranging unit pixels each having a photoelectric converter, a charge-voltage converter, a reset transistor to set the charge-voltage converter to a predetermined potential, and an amplification transistor to read out a signal converted by the charge-voltage converter; a signal processor configured to process a signal output from the unit pixel by using a reference voltage; and a setter configured to set a reset level obtained from a second unit pixel from which a signal level has been already read out as the reference voltage of the signal processor before readout of a signal level based on a signal charge accumulated or retained in the charge-voltage converter from a first unit pixel.Type: ApplicationFiled: March 21, 2011Publication date: February 2, 2012Applicant: Sony CorporationInventors: Yusuke Oike, Akihiko Kato, Takafumi Takatsuka, Masaki Sakakibara
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Publication number: 20110242389Abstract: Disclosed herein is a solid-state imaging device employing a plurality of unit pixels each having an opto-electric conversion section configured to convert incident light into electric charge and an electric-charge holding section configured to hold a signal voltage representing the electric charge produced by the opto-electric conversion section, the solid-state imaging device further including a read section and a control section.Type: ApplicationFiled: March 22, 2011Publication date: October 6, 2011Applicant: Sony CorporationInventors: Takafumi Takatsuka, Akihiko Kato, Yusuke Oike, Masaki Sakakibara
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Publication number: 20110242381Abstract: Disclosed herein is a solid-state image pickup apparatus, including a pixel array section in which a unit pixel including a photoelectric conversion section and a charge detection section for detecting charge generated by photoelectric conversion by the photoelectric conversion section is disposed; a driving section adapted to carry out driving of reading out a signal of the unit pixel divisionally by twice as a first signal and a second signal; and a signal processing section adapted to set the first signal read out first from the unit pixel as a reference voltage for a processable input voltage range of the signal processing section, adjust the reference voltage so that the first and second signals may be included in the input voltage range and carry out signal processing for the first and second signals using the adjusted reference voltage.Type: ApplicationFiled: March 21, 2011Publication date: October 6, 2011Applicant: Sony CorporationInventors: Masaki Sakakibara, Tadayuki Taura, Yusuke Oike, Takafumi Takatsuka, Akihiko Kato
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Publication number: 20100245647Abstract: A solid-state imaging device includes a first chip including a plurality of pixels, each pixel including a light sensing unit generating a signal charge responsive to an amount of received light, and a plurality of MOS transistors reading the signal charge generated by the light sensing unit and outputting the read signal charge as a pixel signal, a second chip including a plurality of pixel drive circuits supplying desired drive pulses to pixels, the second chip being laminated beneath the first chip in a manner such that the pixel drive circuits are arranged beneath the pixels formed in the first chip to drive the pixels, and a connection unit for electrically connecting the pixels to the pixel drive circuits arranged beneath the pixels.Type: ApplicationFiled: March 17, 2010Publication date: September 30, 2010Applicant: SONY CORPORATIONInventors: Katsumi Honda, Takafumi Takatsuka
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Patent number: 7145832Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.Type: GrantFiled: May 8, 2006Date of Patent: December 5, 2006Assignee: Renesas Technology Corp.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
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Publication number: 20060203607Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.Type: ApplicationFiled: May 8, 2006Publication date: September 14, 2006Applicant: RENESAS TECHNOLOGY CORP.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
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Patent number: 7061828Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.Type: GrantFiled: September 1, 2005Date of Patent: June 13, 2006Assignee: Renesas Technology Corp.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
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Publication number: 20060050587Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.Type: ApplicationFiled: September 1, 2005Publication date: March 9, 2006Applicant: Renesas Technology Corp.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
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Patent number: 6956758Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.Type: GrantFiled: February 3, 2005Date of Patent: October 18, 2005Assignee: Renesas Technology Corp.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
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Publication number: 20050141337Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.Type: ApplicationFiled: February 3, 2005Publication date: June 30, 2005Applicant: Renesas Technology Corp.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude