Patents by Inventor Takafumi Takatsuka
Takafumi Takatsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6891770Abstract: Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.Type: GrantFiled: August 18, 2004Date of Patent: May 10, 2005Assignee: Renesas Technology Corp.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
-
Patent number: 6859415Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.Type: GrantFiled: January 28, 2003Date of Patent: February 22, 2005Assignee: Renesas Technology Corp.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
-
Publication number: 20050018529Abstract: Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.Type: ApplicationFiled: August 18, 2004Publication date: January 27, 2005Applicant: RENESAS TECHNOLOGY CORP.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
-
Patent number: 6813211Abstract: Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.Type: GrantFiled: January 15, 2003Date of Patent: November 2, 2004Assignee: Renesas Technology Corp.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
-
Patent number: 6798236Abstract: A semiconductor integrated circuit which is supplied with a first power supply voltage and a second power supply voltage from outside so as to operate incorporated circuits, and outputs data at an output terminal, includes an internal circuit that carries out a predetermined function for an input signal, an output circuit which includes a first circuit for converting the signal from the internal circuit into an output signal and a second circuit containing a final stage buffer circuit which outputs, depending on the signal from the first circuit, data to the output terminal; and a switching circuit that switches a power supply voltage supplied to the second circuit, to either the first power supply voltage or the second power supply voltage. A voltage obtained by decreasing the first power supply voltage is supplied to the internal circuit. The first power supply voltage is supplied to the first circuit.Type: GrantFiled: October 17, 2002Date of Patent: September 28, 2004Assignee: Renesas Technology Corp.Inventors: Tadayuki Shimizu, Takafumi Takatsuka, Masaki Tsukude
-
Patent number: 6744679Abstract: A DRAM performs data writing if a column activation signal ZCOLRE is activated with changing of an internal address Add and then an internal write control signal WDRV is activated by generation of a write signal WE from an outside. However, in order to solve a problem that data writing does not performed in some cases when the data writing is performed at optional timing, a semiconductor memory device according to the present invention includes a delay unit, thereby delaying an output of the internal write control signal WDRV until the column activation signal ZCOLRE is activated, even when the write signal WE is generated.Type: GrantFiled: September 16, 2002Date of Patent: June 1, 2004Assignee: Renesas Technology Corp.Inventors: Hirotoshi Sato, Masaki Tsukude, Takafumi Takatsuka
-
Patent number: 6714047Abstract: The semiconductor integrated circuit incudes an input circuit which receives a signal, an internal circuit which applies a predetermined function to the received signal, and an output circuit which outputs the signal applied with the predetermined function. An external power supply voltage VDD and an IO power supply voltage VDDQ which is lower than the voltage VDD are supplied to the semiconductor integrated circuit. A voltage VIO obtained by decreasing the external power supply voltage VDD is supplied to the input circuit. The IO power supply voltage VDDQ is supplied to the output circuit.Type: GrantFiled: October 9, 2002Date of Patent: March 30, 2004Assignee: Renesas Technology Corp.Inventors: Tadayuki Shimizu, Masaki Tsukude, Takafumi Takatsuka
-
Patent number: 6693838Abstract: A semiconductor memory device such as a pseudo SRAM or the like is provided with a memory cell array being refreshed in accordance with a refresh timing signal having a predetermined refresh period and generated by a refresh timing signal generator circuit. A selector selects a block to hold data in the memory cell array divided into a plurality of blocks in accordance with a predetermined command signal, and a signal generator changes the refresh period according to a number of blocks selected by said selecting means, and generates a refresh timing signal having a changed refresh period and outputs a generated refresh signal.Type: GrantFiled: October 10, 2002Date of Patent: February 17, 2004Assignee: Renesas Technology Corp.Inventors: Tsukasa Hagura, Takafumi Takatsuka, Masaki Tsukude
-
Publication number: 20030198117Abstract: A semiconductor memory device such as a pseudo SRAM or the like is provided with a memory cell array being refreshed in accordance with a refresh timing signal having a predetermined refresh period and generated by a refresh timing signal generator circuit. A selector selects a block to hold data in the memory cell array divided into a plurality of blocks in accordance with a predetermined command signal, and a signal generator changes the refresh period according to a number of blocks selected by said selecting means, and generates a refresh timing signal having a changed refresh period and outputs a generated refresh signal.Type: ApplicationFiled: October 10, 2002Publication date: October 23, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tsukasa Hagura, Takafumi Takatsuka, Masaki Tsukude
-
Publication number: 20030198090Abstract: Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.Type: ApplicationFiled: January 15, 2003Publication date: October 23, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
-
Publication number: 20030193349Abstract: The semiconductor integrated circuit incudes an input circuit which receives a signal, an internal circuit which applies a predetermined function to the received signal, and an output circuit which outputs the signal applied with the predetermined function. An external power supply voltage VDD and an IO power supply voltage VDDQ which is lower than the voltage VDD are supplied to the semiconductor integrated circuit. A voltage VIO obtained by decreasing the external power supply voltage VDD is supplied to the input circuit. The IO power supply voltage VDDQ is supplied to the output circuit.Type: ApplicationFiled: October 9, 2002Publication date: October 16, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tadayuki Shimizu, Masaki Tsukude, Takafumi Takatsuka
-
Publication number: 20030193084Abstract: A semiconductor integrated circuit which is supplied with a first power supply voltage and a second power supply voltage from outside so as to operate incorporated circuits, and outputs data at an output terminal, includes an internal circuit that carries out a predetermined function for an input signal, an output circuit which includes a first circuit for converting the signal from the internal circuit into an output signal and a second circuit containing a final stage buffer circuit which outputs, depending on the signal from the first circuit, data to the output terminal; and a switching circuit that switches a power supply voltage supplied to the second circuit, to either the first power supply voltage or the second power supply voltage. A voltage obtained by decreasing the first power supply voltage is supplied to the internal circuit. The first power supply voltage is supplied to the second circuit.Type: ApplicationFiled: October 17, 2002Publication date: October 16, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tadayuki Shimizu, Takafumi Takatsuka, Masaki Tsukude
-
Publication number: 20030185060Abstract: A DRAM performs data writing if a column activation signal ZCOLRE is activated with changing of an internal address Add and then an internal write control signal WDRV is activated by generation of a write signal WE from an outside. However, in order to solve a problem that data writing does not performed in some cases when the data writing is performed at optional timing, a semiconductor memory device according to the present invention includes a delay unit, thereby delaying an output of the internal write control signal WDRV until the column activation signal ZCOLRE is activated, even when the write signal WE is generated.Type: ApplicationFiled: September 16, 2002Publication date: October 2, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Hirotoshi Sato, Masaki Tsukude, Takafumi Takatsuka
-
Publication number: 20030185079Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.Type: ApplicationFiled: January 28, 2003Publication date: October 2, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
-
Publication number: 20030183926Abstract: A plurality of semiconductor chips are mounted in the same package, and a power supply is shared by the output circuits of the chips. In this case, even though the internal circuit power supplies of the chips are turned off, since an output circuit is in an ON state, a through current may flow from another chip. Therefore, a circuit for setting transistors constituting the output circuits of the chips in high-impedance states when the power supplies for the internal circuits of the respective semiconductor chips are turned off is added.Type: ApplicationFiled: September 24, 2002Publication date: October 2, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tadayuki Shimizu, Masaki Tsukude, Takafumi Takatsuka, Hirotoshi Sato
-
Patent number: 6501693Abstract: A row control circuit includes a selector for outputting, as a signal ZRXTRSTD, either signal INTSIG or ZRXTRST in accordance with a test signal TEST, and a holding circuit for receiving a signal ZRXTS by an input A, receiving the signal ZRXTRSTD by an input B, and outputting a word line activating signal RXT from an output node OUT. In a test mode, the phase relation of a sense amplifier activating signal S0N and the word line active signal RXT is set to be different from that in a normal mode. Consequently, a margin of a timing of reading operation or restoring operation can be evaluated.Type: GrantFiled: November 13, 2001Date of Patent: December 31, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takafumi Takatsuka, Masaki Tsukude
-
Publication number: 20020176295Abstract: A row control circuit includes a selector for outputting, as a signal ZRXTRSTD, either signal INTSIG or ZRXTRST in accordance with a test signal TEST, and a holding circuit for receiving a signal ZRXTS by an input A, receiving the signal ZRXTRSTD by an input B, and outputting a word line activating signal RXT from an output node OUT. In a test mode, the phase relation of a sense amplifier activating signal S0N and the word line active signal RXT is set to be different from that in a normal mode. Consequently, a margin of a timing of reading operation or restoring operation can be evaluated.Type: ApplicationFiled: November 13, 2001Publication date: November 28, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Takafumi Takatsuka, Masaki Tsukude