Patents by Inventor Takafumi Tokunaga
Takafumi Tokunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7737023Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.Type: GrantFiled: August 19, 2008Date of Patent: June 15, 2010Assignee: Renesas Technology CorporationInventors: Shouochi Uno, Atsushi Maekawa, Takashi Yunogami, Kazutami Tago, Kazuo Nojiri, Shuntaro Machida, Takafumi Tokunaga
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Publication number: 20090011592Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.Type: ApplicationFiled: August 19, 2008Publication date: January 8, 2009Inventors: Shouichi Uno, Atsushi Maekawa, Takashi Yunogami, Kazutami Tago, Kazuo Nojiri, Shuntaro Machida, Takafumi Tokunaga
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Patent number: 7427537Abstract: In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, the surfaces of the source and the drain of a MISFET of an indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of a MISFET of the logic integrated circuit, and the silicide layer is not formed on the surfaces of the source and the drain of a memory cell selective MISFET of the memory cell of the DRAM.Type: GrantFiled: August 31, 2006Date of Patent: September 23, 2008Assignee: Renesas Technology Corp.Inventors: Takafumi Tokunaga, Makoto Yoshida, Fumio Ootsuka
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Patent number: 7419902Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.Type: GrantFiled: April 13, 2005Date of Patent: September 2, 2008Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., LtdInventors: Shouochi Uno, Atsushi Maekawa, Takashi Yunogami, Kazutami Tago, Kazuo Nojiri, Shuntaro Machida, Takafumi Tokunaga
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Patent number: 7259104Abstract: A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.Type: GrantFiled: September 29, 2003Date of Patent: August 21, 2007Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Takafumi Tokunaga, Tadashi Umezawa, Motohiko Yoshigai, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takashi Sato, Yasushi Goto
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Publication number: 20060292791Abstract: In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, the surfaces of the source and the drain of a MISFET of an indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of a MISFET of the logic integrated circuit, and the silicide layer is not formed on the surfaces of the source and the drain of a memory cell selective MISFET of the memory cell of the DRAM.Type: ApplicationFiled: August 31, 2006Publication date: December 28, 2006Inventors: Takafumi Tokunaga, Makoto Yoshida, Fumio Ootsuka
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Patent number: 7118949Abstract: In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, the surfaces of the source and the drain of a MISFET of an indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of a MISFET of the logic integrated circuit, and the silicide layer is not formed on the surfaces of the source and the drain of a memory cell selective MISFET of the memory cell of the DRAM.Type: GrantFiled: November 17, 2004Date of Patent: October 10, 2006Assignee: Renesas Technology Corp.Inventors: Takafumi Tokunaga, Makoto Yoshida, Fumio Ootsuka
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Patent number: 7049243Abstract: A plasma processing method for etching a sample having a gate oxide film which generates a plasma in a vacuum chamber using electromagnetic waves, applies an rf bias power to the sample, turns off the rf bias power before a charged voltage of the sample reaches a breakdown voltage of the gate oxide film, turns on the rf bias power after the charged voltage of the sample has substantially dropped and repeats the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time, and the plasma is generated by continuously supplying power to enable generation of the plasma during the repeated turning on and off of the rf bias power.Type: GrantFiled: January 12, 2004Date of Patent: May 23, 2006Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Publication number: 20050186801Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.Type: ApplicationFiled: April 13, 2005Publication date: August 25, 2005Inventors: Shouochi Uno, Atsushi Maekawa, Takashi Yunogami, Kazutami Tago, Kazuo Nojiri, Shuntaro Machida, Takafumi Tokunaga
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Publication number: 20050070099Abstract: In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, the surfaces of the source and the drain of a MISFET of an indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of a MISFET of the logic integrated circuit, and the silicide layer is not formed on the surfaces of the source and the drain of a memory cell selective MISFET of the memory cell of the DRAM.Type: ApplicationFiled: November 17, 2004Publication date: March 31, 2005Inventors: Takafumi Tokunaga, Makoto Yoshida, Fumio Ootsuka
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Patent number: 6849191Abstract: According to the present invention, there is provided a sample surface treating apparatus for processing a fine pattern by plasma etching, including a stage provided in a chamber, on which a sample to be subjected to a surface treatment is placed; etching gas supply source for continuously supplying an etching gas for plasma generation into the chamber; a plasma generator for generating a high-density plasma in the chamber; a bias power supply for applying a bias voltage of 100 kHz or higher to the stage independently of the plasma generation; and a pulse modulator for modulating the bias power supply at a frequency of 100 Hz to 10 kHz, wherein a surface treatment in which the minimum feature size is 1 ?m or smaller is performed on the sample placed on the stage.Type: GrantFiled: February 12, 1999Date of Patent: February 1, 2005Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Tatsumi Mizutani, Ryouji Hamasaki, Tokuo Kure, Takafumi Tokunaga, Masayuki Kojima
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Patent number: 6838320Abstract: In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, the surfaces of the source and the drain of a MISFET of an indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of a MISFET of the logic integrated circuit, and the silicide layer is not formed on the surfaces of the source and the drain of a memory cell selective MISFET of the memory cell of the DRAM.Type: GrantFiled: October 5, 2001Date of Patent: January 4, 2005Assignee: Renesas Technology Corp.Inventors: Takafumi Tokunaga, Makoto Yoshida, Fumio Ootsuka
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Publication number: 20040259361Abstract: A plasma processing method for etching a sample having a gate oxide film which generates a plasma in a vacuum chamber using electromagnetic waves, applies an rf bias power to the sample, turns off the rf bias power before a charged voltage of the sample reaches a breakdown voltage of the gate oxide film, turns on the rf bias power after the charged voltage of the sample has substantially dropped and repeats the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time, and the plasma is generated by continuously supplying power to enable generation of the plasma during the repeated turning on and off of the rf bias power.Type: ApplicationFiled: January 12, 2004Publication date: December 23, 2004Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Patent number: 6791137Abstract: In semiconductor integrated circuit devices having fine memory cells and a reduced bit line capacity, a side wall insulating film of gate electrodes (word line) is made of silicon nitride and a side wall insulating film of silicon oxide having a dielectric constant smaller than that of the side wall insulating film made of silicon nitride, thereby reducing the capacity for a word line formed over the gate electrode (word line). By setting the level of the upper end of the side wall insulating film made of silicon oxide to be lower than that of the top face of a cap insulating film, the diameter in the upper part of a plug buried in each space (contact holes) between the gate electrodes is set larger than the diameter in the bottom part to assure a contact area between the contact hole and a through hole formed on the contact hole.Type: GrantFiled: March 26, 2003Date of Patent: September 14, 2004Assignee: Hitachi, Ltd.Inventors: Satoru Yamada, Kiyonori Oyu, Takafumi Tokunaga, Hiroyuki Enomoto, Toshihiro Sekiguchi
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Patent number: 6767838Abstract: A method and apparatus of treating a surface of a sample. A sample is arranged on a stage provided in a chamber, an etching gas is continuously supplied into the chamber and a plasma is generated from the etching gas. An rf bias at a frequency of 100 kHz or higher is applied to the stage independently of the generation of the plasma, and the rf bias is modulated at a frequency of 100 Hz to 10 kHz. Thereby, a surface treatment in which a minimum feature size is 1 &mgr;m or smaller is performed on the sample.Type: GrantFiled: October 19, 2000Date of Patent: July 27, 2004Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Tatsumi Mizutani, Ryouji Hamasaki, Tokuo Kure, Takafumi Tokunaga, Masayuki Kojima
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Patent number: 6677244Abstract: A plasma processing method for etching a sample having a gate oxide film includes generating a plasma in a vacuum chamber using electromagnetic waves, applying an rf bias power to the sample, turning off the rf bias power before a charged voltage of the sample reaches a breakdown voltage, turning on the rf bias power after the charged voltage of the sample has substantially dropped, and repeating the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time.Type: GrantFiled: May 1, 2002Date of Patent: January 13, 2004Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Patent number: 6660647Abstract: A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.Type: GrantFiled: January 11, 2001Date of Patent: December 9, 2003Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Takafumi Tokunaga, Tadashi Umezawa, Motohiko Yoshigai, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takashi Sato, Yasushi Goto
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Publication number: 20030183941Abstract: In semiconductor integrated circuit devices having fine memory cells and a reduced bit line capacity, a side wall insulating film of gate electrodes (word line) is made of silicon nitride and a side wall insulating film of silicon oxide having a dielectric constant smaller than that of the side wall insulating film made of silicon nitride, thereby reducing the capacity for a word line formed over the gate electrode (word line). By setting the level of the upper end of the side wall insulating film made of silicon oxide to be lower than that of the top face of a cap insulating film, the diameter in the upper part of a plug buried in each space (contact holes) between the gate electrodes is set larger than the diameter in the bottom part to assure a contact area between the contact hole and a through hole formed on the contact hole.Type: ApplicationFiled: March 26, 2003Publication date: October 2, 2003Inventors: Satoru Yamada, Kiyonori Oyu, Takafumi Tokunaga, Hiroyuki Enomoto, Toshihiro Sekiguchi
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Publication number: 20030132198Abstract: According to the present invention, there is provided a sample surface treating apparatus for processing a fine pattern by plasma etching, comprising: a stage provided in a chamber, on which a sample to be subjected to a surface treatment is placed; etching gas supplying means for continuously supplying an etching gas for plasma generation into the chamber; plasma generating means for generating a high-density plasma in the chamber; a bias power supply for applying a bias voltage of 100 kHz or higher to the stage independently of the plasma generation; and pulse modulating means for modulating the bias power supply at a frequency of 100 Hz to 10 kHz, wherein a surface treatment in which the minimum feature size is 1 &mgr;m or smaller is performed to the sample placed on the stand.Type: ApplicationFiled: February 12, 1999Publication date: July 17, 2003Inventors: TETSUO ONO, TATSUMI MIZUTANI, RYOUJI KAMASAKI, TOKUO KURE, TAKAFUMI TOKUNAGA, MASAYUKI KOJIMA
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Patent number: RE39895Abstract: To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.Type: GrantFiled: March 8, 2002Date of Patent: October 23, 2007Assignee: Renesas Technology Corp.Inventors: Takafumi Tokunaga, Sadayuki Okudaira, Tatsumi Mizutani, Kazutami Tago, Hideyuki Kazumi, Ken Yoshioka