Patents by Inventor Takafumi Tokunaga
Takafumi Tokunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6555861Abstract: In semiconductor integrated circuit devices having fine memory cells and a reduced bit line capacity, a side wall insulating film of gate electrodes (word line) is made of silicon nitride and a side wall insulating film of silicon oxide having a dielectric constant smaller than that of the side wall insulating film made of silicon nitride, thereby reducing the capacity for a word line formed over the gate electrode (word line). By setting the level of the upper end of the side wall insulating film made of silicon oxide to be lower than that of the top face of a cap insulating film, the diameter in the upper part of a plug buried in each space (contact holes) between the gate electrodes is set larger than the diameter in the bottom part to assure a contact area between the contact hole and a through hole formed on the contact hole.Type: GrantFiled: January 22, 2001Date of Patent: April 29, 2003Assignee: Hitachi, Ltd.Inventors: Satoru Yamada, Kiyonori Oyu, Takafumi Tokunaga, Hiroyuki Enomoto, Toshihiro Sekiguchi
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Patent number: 6492277Abstract: Electrical damage to semiconductor elements in the plasma etching thereof is suppressed. In processing of a fine pattern by plasma etching, the high frequency power supply to be applied to the specimen is turned off before the charge potential at a portion of the pattern reaches the breakdown voltage of the gate oxide film which is interconnected to said fine pattern, and then the high frequency power supply is turned on when the charge potential at the portion of the pattern drops substantially. This on and off control is effected in a repetitive mode of operation.Type: GrantFiled: September 10, 1999Date of Patent: December 10, 2002Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Publication number: 20020125207Abstract: A plasma processing method for etching a sample includes generating a plasma in a treatment chamber having a stage on which the sample is placed, wherein the plasma is generated by use of electromagnetic waves, applying an rf bias to the stage with a frequency which enables reduction of ions having an intermediate energy, and on-off modulating the rf bias so that reaction products are deposited on the sample during the off period of the rf bias.Type: ApplicationFiled: May 1, 2002Publication date: September 12, 2002Inventors: Tetsuo Ono, Tatsumi Mizutani, Ryouji Hamasaki, Tokuo Kure, Takafumi Tokunaga, Masayuki Kojima
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Publication number: 20020123229Abstract: A plasma processing method for etching a sample having a gate oxide film includes generating a plasma in a vacuum chamber using electromagnetic waves, applying an rf bias power to the sample, turning off the rf bias power before a charged voltage of the sample reaches a breakdown voltage, turning on the rf bias power after the charged voltage of the sample has substantially dropped, and repeating the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time.Type: ApplicationFiled: May 1, 2002Publication date: September 5, 2002Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Publication number: 20020047150Abstract: In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, the surfaces of the source and the drain of a MISFET of an indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of a MISFET of the logic integrated circuit, and the silicide layer is not formed on the surfaces of the source and the drain of a memory cell selective MISFET of the memory cell of the DRAM.Type: ApplicationFiled: October 5, 2001Publication date: April 25, 2002Inventors: Takafumi Tokunaga, Makoto Yoshida, Fumio Ootsuka
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Publication number: 20020043680Abstract: Disclosed is a semiconductor integrated circuit device including a DRAM having fine memory cells and a reduced bit line capacity. A side wall insulating film of a gate electrode (word line) is constructed by a side wall insulating film made of silicon nitride and a side wall insulating film made of silicon oxide having a dielectric constant smaller than that of the side wall insulating film made of silicon nitride, thereby reducing a capacity for a word line of a bit line formed over the gate electrode (word line). By setting the level of the upper end of the side wall insulating film made of silicon oxide to be lower than the level of the top face of a cap insulating film, the diameter in the upper part of a plug buried in each of spaces (contact holes) between the gate electrodes is set to be larger than the diameter in the bottom part to assure a contact area between the contact hole and a through hole formed on the contact hole.Type: ApplicationFiled: January 22, 2001Publication date: April 18, 2002Inventors: Satoru Yamada, Kiyonori Oyu, Takafumi Tokunaga, Hiroyuki Enomoto, Toshihiro Sekiguchi
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Patent number: 6309980Abstract: To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.Type: GrantFiled: May 4, 2000Date of Patent: October 30, 2001Assignee: Hitachi, Ltd.Inventors: Takafumi Tokunaga, Sadayuki Okudaira, Tatsumi Mizutani, Kazutami Tago, Hideyuki Kazumi, Ken Yoshioka
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Patent number: 6191045Abstract: In order to provide a method of treating a multilayer including metal and polysilicon for use in a conductor or a gate electrode of a semiconductor device with high accuracy at a high selectivity, the temperature of a sample is maintained at 100° C. or higher at the time of etching a metal film to increase the etch rate of the metal film. In order to suppress the etch rate of a polysilicon film and prevent side etching, an oxygen gas is added to a gas containing a halogen element. In order to suppress the etch rate of a silicon oxide film at the time of etching the polysilicon film, the etching is performed with etch parameters which are divided into those for the metal film and those for the polysilicon film. In the etching performed to the multilayer containing metal and polysilicon, by etching the metal film at a high temperature of 100° C. or higher, the etch rate of the metal film becomes high. Consequently, there is no partial etch residue of the metal film and a barrier film.Type: GrantFiled: April 30, 1999Date of Patent: February 20, 2001Assignee: Hitachi, Ltd.Inventors: Motohiko Yoshigai, Hiroshi Hasegawa, Hiroshi Akiyama, Takafumi Tokunaga, Tadashi Umezawa, Masayuki Kojima, Kazuo Nojiri, Hiroshi Kawakami, Kunihiko Katou
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Patent number: 6074958Abstract: To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.Type: GrantFiled: June 23, 1999Date of Patent: June 13, 2000Assignee: Hitachi, Ltd.Inventors: Takafumi Tokunaga, Sadayuki Okudaira, Tatsumi Mizutani, Kazutami Tago, Hideyuki Kazumi, Ken Yoshioka
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Patent number: 5972862Abstract: There is disclosed a cleaning liquid for producing a semiconductor device which comprises (A) fluorine-containing compound; (B) water-soluble or water-miscible organic solvent; and (C) inorganic acid and/or organic acid, optionally, further comprises (D) quaternary ammonium salt or (D') a specific organic carboxylic acid ammonium salt and/or an organic carboxylic acid amine salt; as well as a process for producing a semiconductor device by forming a resist pattern on a substrate equipped on the surface with an insulating film layer or a metallic electroconductive layer, forming a via hole or electric wiring by dry etching, removing the resist pattern by ashing treatment with oxygen plasma; and effecting an cleaning treatment with the above cleaning liquid. The above cleaning liquid and production process can readily remove the deposit polymer formed in the case of dry etching without impairing metallic film and insulating film.Type: GrantFiled: July 28, 1997Date of Patent: October 26, 1999Assignee: Mitsubishi Gas ChemicalInventors: Yoshimi Torii, Shunji Sasabe, Masayuki Kojima, Kazuhisa Usuami, Takafumi Tokunaga, Kazusato Hara, Yoshikazu Ohira, Tsuyoshi Matsui, Hideto Gotoh, Tetsuo Aoyama, Ryuji Hasemi, Hidetoshi Ikeda, Fukusaburo Ishihara, Ryuji Sotoaka
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Patent number: 5962347Abstract: To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.Type: GrantFiled: November 10, 1998Date of Patent: October 5, 1999Assignee: Hitachi, Ltd.Inventors: Takafumi Tokunaga, Sadayuki Okudaira, Tatsumi Mizutani, Kazutami Tago, Hideyuki Kazumi, Ken Yoshioka
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Patent number: 5933726Abstract: A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.Type: GrantFiled: August 27, 1996Date of Patent: August 3, 1999Assignee: Texas Instruments IncorporatedInventors: Michio Nishimura, Kazuhiko Saitoh, Masayuki Yasuda, Takashi Hayakawa, Michio Tanaka, Yuji Ezaki, Katsuo Yuhara, Minoru Ohtsuka, Toshikazu Kumai, Songsu Cho, Toshiyuki Kaeriyama, Keizo Kawakita, Toshihiro Sekiguchi, Yoshitaka Tadaki, Jun Murata, Hideo Aoki, Akihiko Konno, Kiyomi Katsuyama, Takafumi Tokunaga, Yoshimi Torii
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Patent number: 5874013Abstract: To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other, and selectively obtaining desired dissociated species.Type: GrantFiled: May 15, 1997Date of Patent: February 23, 1999Assignee: Hitachi, Ltd.Inventors: Takafumi Tokunaga, Sadayuki Okudaira, Tatsumi Mizutani, Kazutami Tago, Hideyuki Kazumi, Ken Yoshioka
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Patent number: 4931410Abstract: Disclosed is a process for forming a patterned copper layer on a substrate, using a patterned photoresist layer for forming the patterned copper layer. Etching mask and anti-oxidizing layers are formed on a copper layer (from which the patterned copper layer is formed) prior to forming the patterned photoresist layer. The uppermost one of the etching mask and anti-oxidizing layers is etched using the patterned photoresist layer as a mask, and then the patterned photoresist layer is removed, by oxygen plasma treatment, with the copper layer covered by the lower one of the etching mask and anti-oxidizing layers. By removing the patterned photoresist layer, by oxygen plasma treatment, while the copper layer is covered, oxidation of the copper layer during the oxygen plasma treatment can be avoided. The patterned copper layer can be an interconnection or wiring of a semiconductor device, formed on a semiconductor substrate having semiconductor elements therein.Type: GrantFiled: August 25, 1988Date of Patent: June 5, 1990Assignee: Hitachi, Ltd.Inventors: Takafumi Tokunaga, Masatoshi Tsuneoka, Koichiro Mizukami