Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

Abstract: According to one embodiment, a memory device includes a stacked structure including a plurality of conductive layers stacked to be apart from each other in a first direction, and a pillar structure including a resistance change portion extending in the first direction in the stacked structure, and a semiconductor portion which extends in the first direction in the stacked structure and which includes a first portion provided along the resistance change portion and a second portion extending from the first portion in at least one direction intersecting the first direction.

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

Abstract: According to one embodiment, a memory device includes: a first variable resistance layer; first and second semiconductor layers being in contact with the first variable resistance layer; a first word line; a second word line being adjacent to the first word line; and a third word line being adjacent to the first and second word lines with the first semiconductor layer, the first variable resistance layer, and the second semiconductor layer interposed therebetween, and provided between the first word line and the second word line. In the first variable resistance layer, a first region including a shortest path connecting the first word line and the third word line functions as a first memory cell, and a second region including a shortest path connecting the third word line and the second word line functions as a second memory cell.

Abstract: According to one embodiment, a memory device includes: a plurality of memory cells stacked in a first direction orthogonal to a substrate and each including a memory element having at least three resistance states and a selector coupled in parallel to the memory element; a bit line electrically coupled to the memory cells and extending in a second direction intersecting the first direction; and a sense amplifier configured to compare a voltage of the bit line with a plurality of reference voltages and sense data stored in the memory cells.

Abstract: According to one embodiment, a memory device includes: a variable resistance memory region; a semiconductor layer; an insulating layer; first and second word lines; and a first select gate line. When information stored in the first memory cell is read, or when information is written into the first memory cell, after a voltage of the first select gate line is set to a first voltage and voltages of the first and second word lines are set to a second voltage, the voltage of the first select gate line is increased from the first voltage to a third voltage. After the voltage of the first select gate line is increased to at least the second voltage, the voltage of the first word line is decreased from the second voltage to the first voltage, and the voltage of the second word line is increased from the second voltage to a fourth voltage.

Abstract: According to one embodiment, a memory device includes a stacked structure including a plurality of conductive layers stacked to be apart from each other in a first direction, and a pillar structure including a resistance change portion extending in the first direction in the stacked structure, and a semiconductor portion which extends in the first direction in the stacked structure and which includes a first portion provided along the resistance change portion and a second portion extending from the first portion in at least one direction intersecting the first direction.

Abstract: According to one embodiment, a memory device includes a memory cell including a resistance change memory element in which a plurality of data values according to resistance are allowed to be set, and a selector element connected to the resistance change memory element in series, a word line supplying a select signal for selecting the resistance change memory element by the selector element to the memory cell, a bit line to which a data signal according to a data value set in the resistance change memory element is read, a load circuit connected to the memory cell in series and functioning as a load, and a comparator circuit which compares a voltage obtained by the load circuit with a plurality of reference voltages.

Abstract: A memory device includes a memory cell and a first select transistor. The memory cell includes a variable resistance memory region, a first semiconductor layer being in contact with the variable resistance memory region, a first insulating layer being in contact with the first semiconductor layer, and a first voltage application electrode being in contact with the first insulating layer. The first select transistor includes a second semiconductor layer, a second insulating layer being in contact with the second semiconductor layer, and a second voltage application electrode extending in the second direction and being in contact with the second insulating layer.

Abstract: According to one embodiment, a memory device includes: a first variable resistance layer; first and second semiconductor layers being in contact with the first variable resistance layer; a first word line; a second word line being adjacent to the first word line; and a third word line being adjacent to the first and second word lines with the first semiconductor layer, the first variable resistance layer, and the second semiconductor layer interposed therebetween, and provided between the first word line and the second word line. In the first variable resistance layer, a first region including a shortest path connecting the first word line and the third word line functions as a first memory cell, and a second region including a shortest path connecting the third word line and the second word line functions as a second memory cell.

Abstract: According to one embodiment, a memory device includes: a plurality of memory cells stacked in a first direction orthogonal to a substrate and each including a memory element having at least three resistance states and a selector coupled in parallel to the memory element; a bit line electrically coupled to the memory cells and extending in a second direction intersecting the first direction; and a sense amplifier configured to compare a voltage of the bit line with a plurality of reference voltages and sense data stored in the memory cells.

Abstract: According to one embodiment, a memory device includes: a variable resistance memory region; a semiconductor layer; an insulating layer; first and second word lines; and a first select gate line. When information stored in the first memory cell is read, or when information is written into the first memory cell, after a voltage of the first select gate line is set to a first voltage and voltages of the first and second word lines are set to a second voltage, the voltage of the first select gate line is increased from the first voltage to a third voltage. After the voltage of the first select gate line is increased to at least the second voltage, the voltage of the first word line is decreased from the second voltage to the first voltage, and the voltage of the second word line is increased from the second voltage to a fourth voltage.

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

Abstract: According to one embodiment, a driver that sequentially supplies a first voltage, a second voltage higher than the first voltage, and the first voltage to the bit line, during the writing operation to the first memory cell. The driver supplies a third voltage to the second word line and a fourth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if a data is a first data. The driver supplies a fifth voltage to the second word line and a sixth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if the data is a second data. At least the sixth voltage is larger than the fourth voltage or the fifth voltage is larger than the third voltage.

Abstract: According to one embodiment, a driver that sequentially supplies a first voltage, a second voltage higher than the first voltage, and the first voltage to the bit line, during the writing operation to the first memory cell. The driver supplies a third voltage to the second word line and a fourth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if a data is a first data. The driver supplies a fifth voltage to the second word line and a sixth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if the data is a second data. At least the sixth voltage is larger than the fourth voltage or the fifth voltage is larger than the third voltage.

Abstract: According to one embodiment, a memory device includes a memory cell including a resistance change memory element in which a plurality of data values according to resistance are allowed to be set, and a selector element connected to the resistance change memory element in series, a word line supplying a select signal for selecting the resistance change memory element by the selector element to the memory cell, a bit line to which a data signal according to a data value set in the resistance change memory element is read, a load circuit connected to the memory cell in series and functioning as a load, and a comparator circuit which compares a voltage obtained by the load circuit with a plurality of reference voltages.

Abstract: According to one embodiment, a nonvolatile memory device includes first and second word lines, first and second bit lines, memory cells each including a resistance change memory element, a global word line including a first global word line portion including a first end portion, a global bit line including a first global bit line portion including a second end portion. The first and second word lines and the first global bit line portion have a first line width and a first line thickness, the first and second bit lines and the first global word line portion have a second line width and a second line thickness.

Abstract: According to one embodiment, a memory device includes a memory cell including a resistance change memory element and a selector element, a word line, a bit line connected to one end of the memory cell, an operational amplifier including a non-inverting input connected to the bit line, an output circuit including a first terminal connected to an output of the operational amplifier, a second terminal connected to the bit line, and a charge/discharge circuit including a capacitor, a charge circuit and a discharge circuit, each including one end connected to an inverting input of the operational amplifier. At the time of falling of a write voltage for the memory cell, a potential of the other end of the memory cell is set higher than a potential of the other end of the discharge circuit.

Abstract: According to one embodiment, a memory device includes a memory cell and a first select transistor. The memory cell includes: a variable resistance memory region; a first semiconductor layer being in contact with the variable resistance memory region; a first insulating layer being in contact with the first semiconductor layer; and a first voltage application electrode being in contact with the first insulating layer. The first select transistor includes: a second semiconductor layer; a second insulating layer being in contact with the second semiconductor layer; and a second voltage application electrode extending in the second direction and being in contact with the second insulating layer.