Abstract: The cell output control apparatus includes a cell time slot allotment circuit for allotting, cells to be transmitted, to cell time slots with the cell transmission intervals changed, a first holder circuit for holding the value of ACR (Allowed Cell Rate), a first calculator circuit for calculating the ratio, LCR (Line Cell Rate)/ACR, a quantizer circuit for quantizing the ratio, LCR/ACR and controlling the allotment of cell time slots on the basis of the quantization error produced by the quantization, a counter for counting the values of cell time slots, a second calculator circuit for calculating the cell time slots for cells, and a second holder circuit for holding the calculated results, whereby it is possible to absorb the quantization error produced when the ratio, LCR/ACR is quantized into an integral value.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: A packet handler includes an interface circuit of an ATM handler corresponding in one-to-one relation to each input/output port of an ATM switch. A switch interface including a disconnection circuit and a distribution circuit controls the cell flow from each interface circuit to a corresponding input port and the cell from the output ports of the ATM switch to each interface circuit. In a set of the interface circuits, one redundant transmission path can be replaced arbitrarily with two nonredundant independant transmission paths. The ATM communication system can thus accomodate redundant transmission paths and nonredundant transmission paths in an arbitrary ratio.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.

Abstract: An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.

Abstract: An ATM handler that sets a switchover indication to a control register according to a system switchover order from a controller such that a switchover indication is supplied to a selector and line interfaces according to an output signal from the register. The setting of a switchover indication synchronize a switchover of an operation to count user cells between the line interfaces of the active and standby systems with a switchover of a stream of input cells to an ATM switch by a selector. A protection period is provided to allow a time after the system switchover according to a transmission delay lag. The line interface related to a delayed phase assigns a bit for stopping counting to cells input during the protection period so that the counting operation is conducted for the cells other than those assigned with the bit for stopping counting. As a result, duplicate of counting cells is prevented and the number of user cells are accurately counted.

Abstract: An ATM switch including ECC encoder circuits each for generating, for an ATM cell as an information symbol, an ECC check symbol and for adding the ECC check symbol thereto, cell partitioning circuits each for subdividing an information field of an ATM cell into N partial cells, for subdividing a check symbol field into M partial cells, and for assigning an identical routing tag to the obtained partial cells (N+M) partial cell switches for respectively routing the (N+M) partial cells in an independent fashion based on the routing tag, and ECC decoder circuits for receiving the (N+M) partial cells thus routed and for achieving an error correction on the received partial cells.

Abstract: An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.

Abstract: An asynchronous transfer mode switching system for improving switching throughput and averting complicated and difficult timing design. In operation, synchronous cell strings from external transmission lines are converted to asynchronous cell strings which are switched by a space-division switch array. The switched asynchronous cell strings are reconverted to synchronous cell strings for output onto external transmission lines. The space-division switch array comprises a plurality of unit switches in stages, each unit switch having input terminals and output terminals. The unit switches each include a timing control circuit that causes a switching operation to start upon detecting two states concurrently: a stored state of a cell to be switched, and a storage-ready state of a destination for the switched cell. The scheme allows the system to operate in an asynchronous manner.

Abstract: The cell output control apparatus includes a cell time slot allotment circuit for allotting, cells to be transmitted, to cell time slots with the cell transmission intervals changed, a first holder circuit for holding the value of ACR (Allowed Cell Rate), a first calculator circuit for calculating the ratio, LCR (Line Cell Rate)/ACR, a quantizer circuit for quantizing the ratio, LCR/ACR and controlling the allotment of cell time slots on the basis of the quantization error produced by the quantization, a counter for counting the values of cell time slots, a second calculator circuit for calculating the cell time slots for cells, and a second holder circuit for holding the calculated results, whereby it is possible to absorb the quantization error produced when the ratio, LCR/ACR is quantized into an integral value.

Abstract: An ATM switch including ECC encoder circuits each for generating, for an ATM cell as an information symbol, an ECC check symbol and for adding the ECC check symbol thereto, cell partitioning circuits each for subdividing an information field of an ATM cell into N partial cells, for subdividing a check symbol field into M partial cells, and for assigning an identical routing tag to the obtained partial cells (N+M) partial cell switches for respectively routing the (N+M) partial cells in an independent fashion based on the routing tag, and ECC decoder circuits for receiving the (N+M) partial cells thus routed and for achieving an error correction on the received partial cells.

Abstract: An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.

Abstract: A packet handler includes an interface circuit of an ATM handler corresponding in one-to-one relation to each input/output port of an ATM switch. A switch interface including a disconnection circuit and a distribution circuit controls the cell flow from each interface circuit to a corresponding input port and the cell from the output ports of the ATM switch to each interface circuit. In a set of interface circuits, one redundant transmission path can be replaced arbitrarily with two nonredundant independent transmission paths. The ATM communication system can thus accommodate redundant transmission paths and nonredundant transmission paths in an arbitrary ratio.

Abstract: An ATM switching system which includes PVC allocation circuits corresponding to output queues is disclosed. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.

Abstract: In a switching system connected between a plurality of input lines and a plurality of output lines, destinations of a plurality of cells incoming from the plurality of input lines are monitored to detect an output line in a congestion state. Upon detection of the output line in an congestion state, congestion information indicating the output line in the congestion state is generated and added to the output cells. An input buffer control circuit derives the congestion information from the received cell, and performs buffering of a cell or cells in an input buffer, which cells are distributed to the output line in the congested state, among cells input from the input line.

Abstract: An ATM switch including ECC encoder circuits each for generating, for an ATM cell as an information symbol, an ECC check symbol and for adding the ECC check symbol thereto, cell partitioning circuits each for subdividing an information field of an ATM cell into N partial cells, for subdividing a check symbol field into M partial cells, and for assigning an identical routing tag to the obtained partial cells (N+M) partial cell switches for respectively routing the (N+M) partial cells in an independent fashion based on the routing tag, and ECC decoder circuits for receiving the (N+M) partial cells thus routed and for achieving an error correction on the received partial cells.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: A switching system for handling a plurality of cells, each cell including a header section and a data section, and for exchanging a communication message contained in the data section of the cell between a plurality of incoming highways and a plurality of outgoing highways according to the data contained in the header section of the cell. The switching system includes a unit for multiplexing the incoming highways in time division, a first memory having addressable storage locations for storing cells received from the multiplexing unit, a unit for demultiplexing and distributing data output from the first memory among a plurality of outgoing highways, a second memory for storing an empty address of an empty storage location of the first memory, a unit for controlling the write and read operations of the first memory in accordance with an empty address stored in the second memory used as write and read addresses, and a unit for detecting an error in at least one of the write address and read address.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.