Abstract: When the external storage itself is replaced by a legitimate old key by a malicious third party, the security IP cannot recognize that it is the old key and can be easily rolled back, that is, the old key is regarded as the legitimate key and operates. An OTP is provided in the SoC, and the version of the key ring is managed in one control table area. Specifically, predetermined information that is updated in synchronization with the key update is written in the management table area of the OTP, and an authentication value is calculated by associating the predetermined information with a key ring including the update key. The calculated authentication value is added and registered when registering the key ring.

Abstract: A semiconductor device and a control method thereof capable of satisfying both security requirements and functional safety requirements while suppressing an increase in the circuit scale. The semiconductor device includes: a first encryptor having a first encryption processing unit that performs encryption process on plaintext data input from the outside to generate the first encryption data; a first decryptor having a first decryption processing unit that performs decryption processing in synchronization with an encryption process in the first encryption device to generate the first decryption data for the first encryption data generated in the first encryptor; a comparator that compares the plaintext data with the first decrypted data corresponding to the plaintext data; and a control unit that performs failure determination for the first encryptor and the first decryptor based on the comparison result by the comparator.

Abstract: A control circuit causes a first cryptographic module to perform a dummy operation in a command processing period and a data processing period in which a second cryptographic module performs a normal operation while the first cryptographic module does not perform a normal operation.

Abstract: A memory device includes a memory core that stores data, an access controlling unit that controls an access to the memory core, and a random number generating unit that generates a random number based on an unstable factor related to an access operation to the memory core performed by the access controlling unit.

Abstract: Circuitry is configured to cause a memory device to perform a predetermined power consumption operation for authentication of the memory device in addition to a normal operation, and determine whether the memory device is an authorized or an unauthorized product, based on a measured current value measured in a period when the memory device performs the power consumption operation and a reference current value that is a current value in the power consumption operation by an authorized product.

Abstract: A host device includes a power supply unit configured to supply power to a SoC, a current measurement circuit configured to measure a current from the power supply unit to the SoC, a detection unit configured to detect a power supply glitch in the host device, on the basis of a result of current measurement by the current measurement circuit, and a controller configured to suspend transmission of encrypted command from the host device to the memory device if the detection unit detects a power supply glitch in the host device.

Abstract: A circuitry is configured to calculate a measured average value based on measured current values obtained in a target period for determination, and determine whether a memory device is an authorized or an unauthorized product, based on a comparison result between a measured average value and a reference average value.

Abstract: The circuitry is configured to determine whether an appurtenance device is an authorized or an unauthorized product, based on a comparison result between a measured current value pattern produced for a predetermined period and a reference current value pattern obtained in advance for the predetermined period.

Abstract: A memory device includes a memory core that stores data, an access controlling unit that controls an access to the memory core, and a random number generating unit that generates a random number based on an unstable factor related to an access operation to the memory core performed by the access controlling unit.

Abstract: A control circuit causes a first cryptographic module to perform a dummy operation in a command processing period and a data processing period in which a second cryptographic module performs a normal operation while the first cryptographic module does not perform a normal operation.

Abstract: A control circuit causes a first cryptographic module to perform a dummy operation in a command processing period and a data processing period in which a second cryptographic module performs a normal operation while the first cryptographic module does not perform a normal operation.

Abstract: A noise generation module generates power consumption noise to conceal the power consumption characteristics of a cryptographic module. The cryptographic module performs first non-linear transformation on received data, and the noise generation module performs second non-linear transformation on received data during the operational period of the first non-linear transformation.

Abstract: A host device includes a power supply unit configured to supply power to a SoC, a current measurement circuit configured to measure a current from the power supply unit to the SoC, a detection unit configured to detect a power supply glitch in the host device, on the basis of a result of current measurement by the current measurement circuit, and a controller configured to suspend transmission of encrypted command from the host device to the memory device if the detection unit detects a power supply glitch in the host device.

Abstract: A circuitry is configured to calculate a measured average value based on measured current values obtained in a target period for determination, and determine whether a memory device is an authorized or an unauthorized product, based on a comparison result between a measured average value and a reference average value.

Abstract: In transmission of command from a host device to a memory device, circuitry is configured to selectively switch between a first pattern and a second pattern. In the first pattern, an encrypted command is generated by encrypting a command with an S-box circuit of a first encryption unit, and the encrypted command is decrypted with an InvS-box circuit of a second decryption unit. In the second pattern, an encrypted command is generated by encrypting a command with an InvS-box circuit of a first decryption unit, and the encrypted command is decrypted with an S-box circuit of a second encryption unit.

Abstract: Circuitry is configured to cause a memory device to perform a predetermined power consumption operation for authentication of the memory device in addition to a normal operation, and determine whether the memory device is an authorized or an unauthorized product, based on a measured current value measured in a period when the memory device performs the power consumption operation and a reference current value that is a current value in the power consumption operation by an authorized product.

Abstract: The circuitry is configured to determine whether an appurtenance device is an authorized or an unauthorized product, based on a comparison result between a measured current value pattern produced for a predetermined period and a reference current value pattern obtained in advance for the predetermined period.

Abstract: A memory controller performs a reliability test only on a memory array out of the memory array and a random number generator on receipt of a memory test command from a testing device while performing a reliability test only on the random number generator out of the memory array and the random number generator on receipt of a random number test command from the testing device.

Abstract: A control circuit of a memory device feeds a first clock received from a transmission control circuit of a host device back to a reception control circuit of the host device as a second clock. The reception control circuit controls data reception from the memory device in synchronization with the fed-back second clock.

Abstract: A random number generating device includes an uncertain circuit which outputs uncertain data, and a cipher processing device. The cipher processing device encrypts input data using a cipher function of the cipher processing device, and generates a random number including higher uniformity than data outputted from said uncertain circuit using the cipher function of the cipher processing device and the data outputted from the uncertain circuit.