Patents by Inventor Takahiko Sugahara

Takahiko Sugahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11115181
    Abstract: A control circuit causes a first cryptographic module to perform a dummy operation in a command processing period and a data processing period in which a second cryptographic module performs a normal operation while the first cryptographic module does not perform a normal operation.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: September 7, 2021
    Assignee: MEGACHIPS CORPORATION
    Inventors: Takahiko Sugahara, Hiromu Yutani
  • Patent number: 11080020
    Abstract: A memory device includes a memory core that stores data, an access controlling unit that controls an access to the memory core, and a random number generating unit that generates a random number based on an unstable factor related to an access operation to the memory core performed by the access controlling unit.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: August 3, 2021
    Assignee: MEGACHIPS CORPORATION
    Inventors: Takahiko Sugahara, Masayuki Imagawa, Hiroki Mizukami, Pan Yang
  • Patent number: 11074370
    Abstract: A host device includes a power supply unit configured to supply power to a SoC, a current measurement circuit configured to measure a current from the power supply unit to the SoC, a detection unit configured to detect a power supply glitch in the host device, on the basis of a result of current measurement by the current measurement circuit, and a controller configured to suspend transmission of encrypted command from the host device to the memory device if the detection unit detects a power supply glitch in the host device.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: July 27, 2021
    Assignee: MEGACHIPS CORPORATION
    Inventors: Takahiko Sugahara, Naoki Matsuyama, Harunobu Kishida
  • Patent number: 11073542
    Abstract: Circuitry is configured to cause a memory device to perform a predetermined power consumption operation for authentication of the memory device in addition to a normal operation, and determine whether the memory device is an authorized or an unauthorized product, based on a measured current value measured in a period when the memory device performs the power consumption operation and a reference current value that is a current value in the power consumption operation by an authorized product.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 27, 2021
    Assignee: MEGACHIPS CORPORATION
    Inventor: Takahiko Sugahara
  • Patent number: 11009535
    Abstract: A circuitry is configured to calculate a measured average value based on measured current values obtained in a target period for determination, and determine whether a memory device is an authorized or an unauthorized product, based on a comparison result between a measured average value and a reference average value.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: May 18, 2021
    Assignee: MEGACHIPS CORPORATION
    Inventors: Takahiko Sugahara, Harunobu Kishida
  • Patent number: 10984092
    Abstract: The circuitry is configured to determine whether an appurtenance device is an authorized or an unauthorized product, based on a comparison result between a measured current value pattern produced for a predetermined period and a reference current value pattern obtained in advance for the predetermined period.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: April 20, 2021
    Assignee: MegaChips Corporation
    Inventors: Takahiko Sugahara, Takeshi Yamamoto
  • Publication number: 20200341734
    Abstract: A memory device includes a memory core that stores data, an access controlling unit that controls an access to the memory core, and a random number generating unit that generates a random number based on an unstable factor related to an access operation to the memory core performed by the access controlling unit.
    Type: Application
    Filed: April 16, 2020
    Publication date: October 29, 2020
    Applicant: MegaChips Corporation
    Inventors: Takahiko SUGAHARA, Masayuki IMAGAWA, Hiroki MIZUKAMI, Pan YANG
  • Publication number: 20200195418
    Abstract: A control circuit causes a first cryptographic module to perform a dummy operation in a command processing period and a data processing period in which a second cryptographic module performs a normal operation while the first cryptographic module does not perform a normal operation.
    Type: Application
    Filed: February 25, 2020
    Publication date: June 18, 2020
    Applicant: MegaChips Corporation
    Inventors: Takahiko SUGAHARA, Hiromu YUTANI
  • Patent number: 10615959
    Abstract: A control circuit causes a first cryptographic module to perform a dummy operation in a command processing period and a data processing period in which a second cryptographic module performs a normal operation while the first cryptographic module does not perform a normal operation.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: April 7, 2020
    Assignee: MEGACHIPS CORPORATION
    Inventors: Takahiko Sugahara, Hiromu Yutani
  • Patent number: 10530567
    Abstract: A noise generation module generates power consumption noise to conceal the power consumption characteristics of a cryptographic module. The cryptographic module performs first non-linear transformation on received data, and the noise generation module performs second non-linear transformation on received data during the operational period of the first non-linear transformation.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: January 7, 2020
    Assignee: MEGACHIPS CORPORATION
    Inventors: Takahiko Sugahara, Hiromu Yutani, Hajime Yoshimura, Masayuki Imagawa
  • Publication number: 20190278945
    Abstract: A host device includes a power supply unit configured to supply power to a SoC, a current measurement circuit configured to measure a current from the power supply unit to the SoC, a detection unit configured to detect a power supply glitch in the host device, on the basis of a result of current measurement by the current measurement circuit, and a controller configured to suspend transmission of encrypted command from the host device to the memory device if the detection unit detects a power supply glitch in the host device.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 12, 2019
    Applicant: MegaChips Corporation
    Inventors: Takahiko SUGAHARA, Naoki MATSUYAMA, Harunobu KISHIDA
  • Publication number: 20190199526
    Abstract: In transmission of command from a host device to a memory device, circuitry is configured to selectively switch between a first pattern and a second pattern. In the first pattern, an encrypted command is generated by encrypting a command with an S-box circuit of a first encryption unit, and the encrypted command is decrypted with an InvS-box circuit of a second decryption unit. In the second pattern, an encrypted command is generated by encrypting a command with an InvS-box circuit of a first decryption unit, and the encrypted command is decrypted with an S-box circuit of a second encryption unit.
    Type: Application
    Filed: December 27, 2018
    Publication date: June 27, 2019
    Applicant: MegaChips Corporation
    Inventors: Takahiko SUGAHARA, Naoki MATSUYAMA
  • Publication number: 20190195925
    Abstract: A circuitry is configured to calculate a measured average value based on measured current values obtained in a target period for determination, and determine whether a memory device is an authorized or an unauthorized product, based on a comparison result between a measured average value and a reference average value.
    Type: Application
    Filed: December 24, 2018
    Publication date: June 27, 2019
    Applicant: MegaChips Corporation
    Inventors: Takahiko SUGAHARA, Harunobu KISHIDA
  • Publication number: 20190188372
    Abstract: The circuitry is configured to determine whether an appurtenance device is an authorized or an unauthorized product, based on a comparison result between a measured current value pattern produced for a predetermined period and a reference current value pattern obtained in advance for the predetermined period.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 20, 2019
    Applicant: MegaChips Corporation
    Inventors: Takahiko Sugahara, Takeshi Yamamoto
  • Publication number: 20190187194
    Abstract: Circuitry is configured to cause a memory device to perform a predetermined power consumption operation for authentication of the memory device in addition to a normal operation, and determine whether the memory device is an authorized or an unauthorized product, based on a measured current value measured in a period when the memory device performs the power consumption operation and a reference current value that is a current value in the power consumption operation by an authorized product.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 20, 2019
    Applicant: MegaChips Corporation
    Inventor: Takahiko SUGAHARA
  • Publication number: 20190006023
    Abstract: A memory controller performs a reliability test only on a memory array out of the memory array and a random number generator on receipt of a memory test command from a testing device while performing a reliability test only on the random number generator out of the memory array and the random number generator on receipt of a random number test command from the testing device.
    Type: Application
    Filed: September 10, 2018
    Publication date: January 3, 2019
    Applicant: MegaChips Corporation
    Inventor: Takahiko SUGAHARA
  • Patent number: 10152437
    Abstract: A control circuit of a memory device feeds a first clock received from a transmission control circuit of a host device back to a reception control circuit of the host device as a second clock. The reception control circuit controls data reception from the memory device in synchronization with the fed-back second clock.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: December 11, 2018
    Assignee: MegaChips Corporation
    Inventor: Takahiko Sugahara
  • Patent number: 10148434
    Abstract: A random number generating device includes an uncertain circuit which outputs uncertain data, and a cipher processing device. The cipher processing device encrypts input data using a cipher function of the cipher processing device, and generates a random number including higher uniformity than data outputted from said uncertain circuit using the cipher function of the cipher processing device and the data outputted from the uncertain circuit.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: December 4, 2018
    Assignee: MegaChips Corporation
    Inventor: Takahiko Sugahara
  • Patent number: 10096379
    Abstract: A memory controller performs a reliability test only on a memory array out of the memory array and a random number generator on receipt of a memory test command from a testing device while performing a reliability test only on the random number generator out of the memory array and the random number generator on receipt of a random number test command from the testing device.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: October 9, 2018
    Assignee: MegaChips Corporation
    Inventor: Takahiko Sugahara
  • Patent number: 9959403
    Abstract: The communication device sends an authentication code (N) to a semiconductor memory to instruct the semiconductor memory to authenticate the communication device. The semiconductor memory authenticates the communication device based on the authentication code (N), and if the communication device is determined to be valid, sends an authentication code (N+1) to the communication device to instruct the communication device to authenticate the semiconductor memory in response to the authentication code (N). The communication device authenticates the semiconductor memory based on the authentication code (N+1).
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: May 1, 2018
    Assignee: MegaChips Corporation
    Inventor: Takahiko Sugahara