Patents by Inventor Takahiro Kumakawa
Takahiro Kumakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7808059Abstract: In a semiconductor substrate 1, a plurality of semiconductor elements 2 having diaphragm structures are formed in the form of cells in the longitudinal direction and the lateral direction, and V-grooves 3 are formed by anisotropic etching continuously on only division lines 4 parallel formed in one direction, out of the division lines 4 which are orthogonal to each other and divide the respective semiconductor elements 2 individually.Type: GrantFiled: May 2, 2007Date of Patent: October 5, 2010Assignee: Panasonic CorporationInventor: Takahiro Kumakawa
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Patent number: 7754584Abstract: In a semiconductor substrate 1, a plurality of semiconductor elements 2 having diaphragm structures are formed in the form of cells in the longitudinal direction and the lateral direction, and V-grooves 3 are formed by anisotropic etching continuously on only division lines 4 parallel formed in one direction, out of the division lines 4 which are orthogonal to each other and divide the respective semiconductor elements 2 individually.Type: GrantFiled: September 30, 2009Date of Patent: July 13, 2010Assignee: Panasonic CorporationInventor: Takahiro Kumakawa
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Publication number: 20100148315Abstract: A semiconductor wafer includes a plurality of predetermined separation lines extending from an upper surface to a bottom surface; and a semiconductor substrate including a plurality of chip regions segmented by the predetermined separation lines. Tensile stress is applied to regions of the semiconductor substrate provided with the predetermined separation lines.Type: ApplicationFiled: February 25, 2010Publication date: June 17, 2010Applicant: PANASONIC CORPORATIONInventors: Takahiro KUMAKAWA, Hideki KOJIMA, Tomoaki FURUKAWA
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Publication number: 20100022046Abstract: A method for fabricating a semiconductor device includes: the step (a) of forming a vibrating film on a predetermined region of each of a plurality of chips included in a semiconductor wafer; the step (b) of forming, on the semiconductor wafer, an intermediate film containing a sacrifice layer located on the vibrating film of each of the chips; and the step (c) of forming a fixed film on the intermediate film. This method further includes, after the step (c), the step (d) of subjecting the semiconductor wafer to blade dicing to separate the chips, and the step (e) of removing, by etching, the sacrifice layer to provide a cavity between the vibrating film and the fixed film.Type: ApplicationFiled: October 13, 2009Publication date: January 28, 2010Applicant: PANASONIC CORPORATIONInventors: Masaki UTSUMI, Takahiro Kumakawa, Masami Matsuura, Yoshihiro Matsushima
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Publication number: 20100015781Abstract: In a semiconductor substrate 1, a plurality of semiconductor elements 2 having diaphragm structures are formed in the form of cells in the longitudinal direction and the lateral direction, and V-grooves 3 are formed by anisotropic etching continuously on only division lines 4 parallel formed in one direction, out of the division lines 4 which are orthogonal to each other and divide the respective semiconductor elements 2 individually.Type: ApplicationFiled: September 30, 2009Publication date: January 21, 2010Applicant: Panasonic CorporationInventor: Takahiro Kumakawa
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Publication number: 20090218660Abstract: A semiconductor substrate (1) includes a plurality of semiconductor elements (2) in which functional elements are constructed and which is formed in a grid pattern, wherein continuous linear grooves (3) are formed on longitudinal and lateral separating lines (4) that individually separate the plurality of semiconductor elements (2) with the exception of intersections of the separating lines (4) and portions corresponding to corners of each semiconductor element (2).Type: ApplicationFiled: February 24, 2009Publication date: September 3, 2009Applicant: Panasonic CorporationInventors: Masaki Utsumi, Takahiro Kumakawa
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Publication number: 20090108410Abstract: A semiconductor device includes a semiconductor substrate, a diffusion layer conductive film formed on the semiconductor substrate, an interlayer insulating film layered on the semiconductor substrate, an interconnect pattern and a via pattern formed in the interlayer insulating film, a plurality of circuit regions formed in the semiconductor substrate, and a scribe region formed around the circuit regions and separating the circuit regions from each other. The diffusion layer conductive film is not formed at least in a region to which laser light is emitted in the scribe region.Type: ApplicationFiled: June 11, 2008Publication date: April 30, 2009Inventors: Koji Takemura, Takahiro Kumakawa, Yoshihiro Matsushima
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Publication number: 20080203538Abstract: A plurality of semiconductor elements and division regions are provided on a semiconductor subsubstrate. A modification region is provided in the semiconductor substrate. A division guide pattern is provided at least in a portion of each division region. A cleavage produced from a starting point corresponding to the modification region is guided by the division guide pattern.Type: ApplicationFiled: April 28, 2008Publication date: August 28, 2008Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Takahiro Kumakawa, Masaki Utsumi, Yoshihiro Matsushima, Masami Matsuura
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Publication number: 20080135975Abstract: A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor element 2 and a semiconductor substrate 1 and from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.Type: ApplicationFiled: December 6, 2007Publication date: June 12, 2008Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yukiko Haraguchi, Takahiro Kumakawa, Takashi Yui, Kazumi Watase
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Publication number: 20070287215Abstract: A method for fabricating a semiconductor device includes: the step (a) of forming a vibrating film on a predetermined region of each of a plurality of chips included in a semiconductor wafer; the step (b) of forming, on the semiconductor wafer, an intermediate film containing a sacrifice layer located on the vibrating film of each of the chips; and the step (c) of forming a fixed film on the intermediate film. This method further includes, after the step (c), the step (d) of subjecting the semiconductor wafer 101 to blade dicing to separate the chips, and the step (e) of removing, by etching, the sacrifice layer to provide a cavity between the vibrating film and the fixed film.Type: ApplicationFiled: May 16, 2007Publication date: December 13, 2007Inventors: Masaki Utsumi, Takahiro Kumakawa, Masami Matsuura, Yoshihiro Matsushima
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Publication number: 20070264803Abstract: In a semiconductor substrate 1, a plurality of semiconductor elements 2 having diaphragm structures are formed in the form of cells in the longitudinal direction and the lateral direction, and V-grooves 3 are formed by anisotropic etching continuously on only division lines 4 parallel formed in one direction, out of the division lines 4 which are orthogonal to each other and divide the respective semiconductor elements 2 individually.Type: ApplicationFiled: May 2, 2007Publication date: November 15, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Takahiro Kumakawa
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Publication number: 20060163699Abstract: A plurality of semiconductor elements and division regions are provided on a semiconductor substrate. A modification region is provided in the semiconductor substrate. A division guide pattern is provided at least in a portion of each division region. A cleavage produced from a starting point corresponding to the modification region is guided by the division guide pattern.Type: ApplicationFiled: November 29, 2005Publication date: July 27, 2006Inventors: Takahiro Kumakawa, Masaki Utsumi, Yoshihiro Matsushima, Masami Matsuura
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Patent number: 6924173Abstract: Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.Type: GrantFiled: March 14, 2003Date of Patent: August 2, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazumi Watase, Hiroaki Fujimoto, Ryuichi Sahara, Nozomi Shimoishizaka, Takahiro Kumakawa, Kazuyuki Kaino, Yoshifumi Nakamura
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Patent number: 6852616Abstract: A first element electrode and a second element electrode connected electrically to a semiconductor element on a substrate are formed, and then an insulating film is formed on the substrate including the element electrodes. Thereafter, a first opening for exposing the first element electrode and a second opening for exposing the second element electrode are formed on the insulating film. Then, a first external electrode connected to the first element electrode via the first opening is formed immediately above the first element electrode. Furthermore, a second external electrode and a connecting wire having one end connected to the second element electrode via the second opening and the other end connected to the second external electrode are formed on the insulating film.Type: GrantFiled: June 10, 2002Date of Patent: February 8, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ryuichi Sahara, Kazumi Watase, Takahiro Kumakawa, Kazuyuki Kainoh, Nozomi Shimoishizaka
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Publication number: 20050006749Abstract: A low elasticity layer (20) having an opening in an electrode arranging area where element electrodes are disposed is provided on a main surface of a semiconductor substrate (10). On the low elasticity layer (20), lands (32) serving as external electrodes are disposed, and pads (30) on the element electrodes, the lands (32) and metal wires (31) for connecting them are integrally formed as a metal wiring pattern (33). A solder resist film (50) having an opening for exposing a part of each land (32) is formed, and a metal ball (40) is provided on the land (32) in the opening. The low elasticity layer (20) absorbs thermal stress and the like caused in heating or cooling the semiconductor device, so as to prevent disconnection of the metal wires (31).Type: ApplicationFiled: August 12, 2004Publication date: January 13, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Nozomi Shimoishizaka, Ryuichi Sahara, Yoshifumi Nakamura, Takahiro Kumakawa, Shinji Murakami, Yutaka Harada
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Patent number: 6812573Abstract: A low elasticity layer (20) having an opening in an electrode arranging area where element electrodes are disposed is provided on a main surface of a semiconductor substrate (10). On the low elasticity layer (20), lands (32) serving as external electrodes are disposed, and pads (30) on the element electrodes, the lands (32) and metal wires (31) for connecting them are integrally formed as a metal wiring pattern (33). A solder resist film (50) having an opening for exposing a part of each land (32) is formed, and a metal ball (40) is provided on the land (32) in the opening. The low elasticity layer (20) absorbs thermal stress and the like caused in heating or cooling the semiconductor device, so as to prevent disconnection of the metal wires (31).Type: GrantFiled: June 25, 2001Date of Patent: November 2, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Nozomi Shimoishizaka, Ryuichi Sahara, Yoshifumi Nakamura, Takahiro Kumakawa, Shinji Murakami, Yutaka Harada
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Publication number: 20030194834Abstract: Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.Type: ApplicationFiled: March 14, 2003Publication date: October 16, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kazumi Watase, Hiroaki Fujimoto, Ryuichi Sahara, Nozomi Shimoishizaka, Takahiro Kumakawa, Kazuyuki Kaino, Yoshifumi Nakamura
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Patent number: 6559528Abstract: Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.Type: GrantFiled: February 20, 2001Date of Patent: May 6, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazumi Watase, Hiroaki Fujimoto, Ryuichi Sahara, Nozomi Shimoishizaka, Takahiro Kumakawa, Kazuyuki Kaino, Yoshifumi Nakamura
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Patent number: 6512298Abstract: A first element electrode and a second element electrode connected electrically to a semiconductor element on a substrate are formed, and then an insulating film is formed on the substrate including the element electrodes. Thereafter, a first opening for exposing the first element electrode and a second opening for exposing the second element electrode are formed on the insulating film. Then, a first external electrode connected to the first element electrode via the first opening is formed immediately above the first element electrode. Furthermore, a second external electrode and a connecting wire having one end connected to the second element electrode via the second opening and the other end connected to the second external electrode are formed on the insulating film.Type: GrantFiled: October 29, 2001Date of Patent: January 28, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ryuichi Sahara, Kazumi Watase, Takahiro Kumakawa, Kazuyuki Kainoh, Nozomi Shimoishizaka
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Publication number: 20020151104Abstract: A first element electrode and a second element electrode connected electrically to a semiconductor element on a substrate are formed, and then an insulating film is formed on the substrate including the element electrodes. Thereafter, a first opening for exposing the first element electrode and a second opening for exposing the second element electrode are formed on the insulating film. Then, a first external electrode connected to the first element electrode via the first opening is formed immediately above the first element electrode. Furthermore, a second external electrode and a connecting wire having one end connected to the second element electrode via the second opening and the other end connected to the second external electrode are formed on the insulating film.Type: ApplicationFiled: June 10, 2002Publication date: October 17, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Ryuichi Sahara, Kazumi Watase, Takahiro Kumakawa, Kazuyuki Kainoh, Nozomi Shimoishizaka