Abstract: A symbol power tracking amplification system including: a modem to generate data and symbol tracking signals; a symbol tracking modulator including a control circuit, first and second voltage supply circuits and a switch circuit, the control circuit generates first and second voltage level control signals in response to the symbol tracking signal, the first voltage supply circuit generates a first output voltage in response to the first voltage level control signal, the second voltage supply circuit generates a second output voltage in response to the second voltage level control signal and the switch circuit outputs the first or second output voltages as a supply voltage in response to a switch control signal; an RF block to generate an RF signal based on the data signal from the modem; and a power amplifier to adjust a power level of the RF signal based on the supply voltage.

Abstract: According to some example embodiments, an apparatus includes a buck-boost converter, a first buck converter connected at an output terminal of the buck-boost converter, a second buck converter connected at the output terminal of the buck-boost converter, a first LA including a first supply voltage input connected to the output terminal of the buck-boost converter, and an output terminal connected to an output terminal of the first buck converter, where the first LA is configured to provide a first modulated supply voltage to a first PA of a first transmitter, and a second LA including a second supply voltage input connected to the output terminal of the buck-boost converter, and an output terminal connected to an output terminal of the second buck converter, where the second LA is configured to provide a second modulated supply voltage to a second PA of a second transmitter.

Abstract: Provided are a semiconductor device and a method of operating the same. A semiconductor device may include a comparator which compares a first voltage with a rectified voltage and provides a second voltage in accordance with the comparison. A timer circuit may operate a timer according to the second voltage and output a third voltage in correspondence with an operation time of the timer. A driver may drive a transistor with a fourth voltage generated by the driver according to the third voltage. A calibration circuit may generate a timer calibration signal based on the second voltage and the fourth voltage. The timer calibration signal may be provided to the timer circuit and used to calibrate the operation time of the timer. More efficient rectification, with reduced occurrence of reverse current, may thereby be realized.

Abstract: A power converting circuit includes a voltage converting circuit, a feedback circuit, a driving signal generator, a transient state detector, and a resistance value adjuster. The voltage converting circuit changes a voltage level of an input voltage responsive to a driving signal, and outputs an output voltage according to the changed voltage level of the input voltage. The feedback circuit divides the output voltage to output the divided output voltage as a feedback voltage. The driving signal generator compares a level of the feedback voltage with a level of a reference voltage and outputs the driving signal. The transient state detector compares the level of the feedback voltage with the level of the reference voltage and outputs a transient state signal corresponding to a transient state of the output voltage. The resistance value adjuster adjusts the feedback resistance value, which divides the output voltage, responsive to the transient state signal.

Abstract: A voltage regulator includes a high duty cycle detector, a feedback controller, a hysteretic comparator, and first and second drivers. The high duty cycle detector generates a high duty cycle signal based on a power supply voltage and a reference voltage. The feedback controller generates first and second feedback voltages based on the reference voltage, the high duty cycle signal and an output voltage of the voltage regulator. The hysteretic comparator compares the reference voltage and the first feedback voltage to generate a control signal. When the first feedback voltage is activated, the first driver drives an output node that provides the output voltage based on the control signal and the high duty cycle signal. When the second feedback voltage is activated, the second driver generates a third voltage proportional to the reference voltage based on the power supply voltage and the second feedback voltage, and drives the output node with the third voltage.

Abstract: A voltage regulator includes a high duty cycle detector, a feedback controller, a hysteretic comparator, and first and second drivers. The high duty cycle detector generates a high duty cycle signal based on a power supply voltage and a reference voltage. The feedback controller generates first and second feedback voltages based on the reference voltage, the high duty cycle signal and an output voltage of the voltage regulator. The hysteretic comparator compares the reference voltage and the first feedback voltage to generate a control signal. When the first feedback voltage is activated, the first driver drives an output node that provides the output voltage based on the control signal and the high duty cycle signal. When the second feedback voltage is activated, the second driver generates a third voltage proportional to the reference voltage based on the power supply voltage and the second feedback voltage, and drives the output node with the third voltage.

Abstract: A power converting circuit includes a voltage converting circuit, a feedback circuit, a driving signal generator, a transient state detector, and a resistance value adjuster. The voltage converting circuit changes a voltage level of an input voltage in response to a driving signal, and outputs an output voltage according to the changed voltage level of the input voltage. The feedback circuit divides the output voltage to output the divided output voltage as a feedback voltage. The driving signal generator compares a level of the feedback voltage with a level of a reference voltage and outputs the driving signal. The transient state detector compares the level of the feedback voltage with the level of the reference voltage and outputs a transient state signal corresponding to a transient state of the output voltage. The resistance value adjuster adjusts the feedback resistance value, which divides the output voltage, in response to the transient state signal.

Abstract: A switching loss is reduced by reducing a deviation from the operational principle of zero-volt switching (ZVS). A semiconductor integrated circuit includes high-side switch elements Q11 and Q12, a low-side switch element Q2, and a controller CNT. A decoupling capacitance Cin is coupled between one end of a high-side element and an earth potential, and the high-side element includes the first and second transistors Q11 and Q12 coupled in parallel. In changing the high-side elements from an on-state to an off-state, CNT controls Q12 from an on-state to an off-state by delaying Q12 relative to Q11. Q11 and Q12 are divided into a plurality of parts inside a semiconductor chip Chip 1, a plurality of partial first transistors formed by dividing Q11 and a plurality of partial second transistors formed by dividing Q12 are alternately arranged in an arrangement direction of Q11 and Q12, inside the semiconductor chip Chip 1.

Abstract: Disclosed is a power conversion circuit that suppresses the flow of a through current to a switching element based on a normally-on transistor. The power conversion circuit includes a high-side transistor and a low-side transistor, which are series-coupled to each other to form a half-bridge circuit, and two drive circuits, which complementarily drive the gate of the high-side transistor and of the low-side transistor. The high-side transistor is a normally-off transistor. The low-side transistor is a normally-on transistor.

Abstract: Disclosed is a power conversion circuit that suppresses the flow of a through current to a switching element based on a normally-on transistor. The power conversion circuit includes a high-side transistor and a low-side transistor, which are series-coupled to each other to form a half-bridge circuit, and two drive circuits, which complementarily drive the gate of the high-side transistor and of the low-side transistor. The high-side transistor is a normally-off transistor. The low-side transistor is a normally-on transistor.

Abstract: A switching loss is reduced by reducing a deviation from the operational principle of zero-volt switching (ZVS). A semiconductor integrated circuit includes high-side switch elements Q11 and Q12, a low-side switch element Q2, and a controller CNT. A decoupling capacitance Cin is coupled between one end of a high-side element and an earth potential, and the high-side element includes the first and second transistors Q11 and Q12 coupled in parallel. In changing the high-side elements from an on-state to an off-state, CNT controls Q12 from an on-state to an off-state by delaying Q12 relative to Q11. Q11 and Q12 are divided into a plurality of parts inside a semiconductor chip Chip 1, a plurality of partial first transistors formed by dividing Q11 and a plurality of partial second transistors formed by dividing Q12 are alternately arranged in an arrangement direction of Q11 and Q12, inside the semiconductor chip Chip 1.

Abstract: Disclosed is a power conversion circuit that suppresses the flow of a through current to a switching element based on a normally-on transistor. The power conversion circuit includes a high-side transistor and a low-side transistor, which are series-coupled to each other to form a half-bridge circuit, and two drive circuits, which complementarily drive the gate of the high-side transistor and of the low-side transistor. The high-side transistor is a normally-off transistor. The low-side transistor is a normally-on transistor.

Abstract: In a semiconductor device provided with terminals for external connection, input terminals, power supply terminals and ground terminals are disposed close together on part of one edge portion of two opposing edge portions. Output terminals are disposed in the vicinity of both ends of the one edge portion and on another edge portion of the two edge portions. A ground wiring is routed from the other edge portion and connected to the ground terminals. In so doing, elemental devices connected to the input terminals are disposed close together, whereby needless gaps do not arise between the elemental devices. A ground potential is also supplied by the ground wiring.

Abstract: Wiring of a PDP address driver IC is disclosed which affords an adequate permitted current capacity. In the PDP address driver IC that drives the PDP, a layer, in which a planar high voltage ground wiring layer and a planar high voltage power wiring layer are formed, is provided atop a layer in which planar high voltage ground wiring layers that supply a ground potential to the active element that is formed within the PDP address driver IC and in which planar high voltage power wiring layers that supply a source potential to the active element are formed. Accordingly, the PDP address driver IC can comprise an adequate permitted current capacity while maintaining a compact size and comprising a multiplicity of output bit portions.

Abstract: Providing a data compression method, program, and apparatus that allows coding by detecting a repetition of a matching character string even without successiveness of the same numbers in a recent match position list. Using a recent match position list for narrowing down candidates for a matching character string that have previously appeared and to perform detection and coding of a matching character string by performing comparison with each character string in the input buffer as a candidate.

Abstract: Wiring of a PDP address driver IC is disclosed which affords an adequate permitted current capacity. In the PDP address driver IC that drives the PDP, a layer, in which a planar high voltage ground wiring layer and a planar high voltage power wiring layer are formed, is provided atop a layer in which planar high voltage ground wiring layers that supply a ground potential to the active element that is formed within the PDP address driver IC and in which planar high voltage power wiring layers that supply a source potential to the active element are formed. Accordingly, the PDP address driver IC can comprise an adequate permitted current capacity while maintaining a compact size and comprising a multiplicity of output bit portions.

Abstract: In a semiconductor device provided with terminals for external connection, input terminals, power supply terminals and ground terminals are disposed close together on part of one edge portion of two opposing edge portions. Output terminals are disposed in the vicinity of both ends of the one edge portion and on another edge portion of the two edge portions. A ground wiring is routed from the other edge portion and connected to the ground terminals. In so doing, elemental devices connected to the input terminals are disposed close together, whereby needless gaps do not arise between the elemental devices. A ground potential is also supplied by the ground wiring.

Abstract: A recent match position list is used for narrowing down candidates for a matching character string that have previously appeared. With a character string of each candidate in an input buffer being compared, a matching character string is detected and coded. An input unit inputs and retains in the input buffer a data string to be compressed. A recent-match-position-list generating unit generates and retains a recent match position list having stored therein a relative position where a character string having a predetermined length starting at each address in the input buffer has most recently appeared. A repetition candidate acquiring unit uses the recent match position list to acquire a repetition candidate for a position where a character string at a coding position has previously appeared.