Patents by Inventor Takahiro Onodera
Takahiro Onodera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9880589Abstract: An instrument eject system includes a device configured to store an instrument at a storage location within the device. A cover is rotationally coupled to a base via hinge. An ejection element is configured to impose an ejecting force on the instrument when the instrument is stored within the device. A retaining element is configured to retain the instrument within the device in a lock position of the retaining element and to release the instrument in a release position of the retaining element.Type: GrantFiled: June 10, 2016Date of Patent: January 30, 2018Assignee: LENOVO (SINGAPORE) PTE. LTD.Inventors: Hiroyuki Noguchi, Takahiro Onodera
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Publication number: 20170357290Abstract: Disclosed is an eject system for an instrument such as a stylus, comprising an ejection element configured to eject the instrument from a storage location in the device, upon rotation of a cover of the device.Type: ApplicationFiled: June 10, 2016Publication date: December 14, 2017Applicant: LENOVO (SINGAPORE) PTE. LTD.Inventors: Hiroyuki Noguchi, Takahiro Onodera
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Patent number: 8492266Abstract: Provided is a semiconductor device, which includes an interlayer insulating film formed on a semiconductor substrate, a wiring layer filled in a recess formed in the interlayer insulating film, and a cap insulating film. The interlayer insulating film includes a first SiOCH film and a surface modification layer including an SiOCH film formed by modifying a surface layer of the first SiOCH film, the SiOCH film having a lower carbon concentration and a higher oxygen concentration than the first SiOCH film has. The cap insulating film contacts with surfaces of the metal wiring and the surface modification layer.Type: GrantFiled: November 22, 2011Date of Patent: July 23, 2013Assignee: Renesas Electronics CorporationInventors: Makoto Ueki, Takahiro Onodera, Yoshihiro Hayashi
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Patent number: 8198730Abstract: A semiconductor device has a multilayer interconnection including a copper interconnection film formed in a predetermined area within an insulating film, a liner film, and a high-melting-point metal film. The copper interconnection film is polycrystalline, and crystal grains occupying 40% or more of an area of a unit interconnection surface among crystal grains forming the polycrystal are oriented to (111) in a substrate thickness direction. The copper interconnection film has crystal conformity with the noble metal liner film. In a case where the high-melting-point metal film is formed of Ti and the noble metal liner film is a Ru film, the high-melting-point metal of Ti dissolves into Ru in a solid state to form the noble metal liner. Thus, a copper interconnection is formed with both of Cu diffusion barrier characteristics and Cu crystal conformity.Type: GrantFiled: January 8, 2008Date of Patent: June 12, 2012Assignee: NEC CorporationInventors: Masayoshi Tagami, Yoshihiro Hayashi, Munehiro Tada, Takahiro Onodera, Naoya Furutake, Makoto Ueki, Mari Amano
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Publication number: 20120070986Abstract: Provided is a semiconductor device, which includes an interlayer insulating film formed on a semiconductor substrate, a wiring layer filled in a recess formed in the interlayer insulating film, and a cap insulating film. The interlayer insulating film includes a first SiOCH film and a surface modification layer including an SiOCH film formed by modifying a surface layer of the first SiOCH film, the SiOCH film having a lower carbon concentration and a higher oxygen concentration than the first SiOCH film has. The cap insulating film contacts with surfaces of the metal wiring and the surface modification layer.Type: ApplicationFiled: November 22, 2011Publication date: March 22, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Makoto UEKI, Takahiro ONODERA, Yoshihiro HAYASHI
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Patent number: 8080878Abstract: Provided is a semiconductor device, which includes an interlayer insulating film formed on a semiconductor substrate, a wiring layer filled in a recess formed in the interlayer insulating film, and a cap insulating film. The interlayer insulating film includes a first SiOCH film and a surface modification layer including an SiOCH film formed by modifying a surface layer of the first SiOCH film, the SiOCH film having a lower carbon concentration and a higher oxygen concentration than the first SiOCH film has. The cap insulating film contacts with surfaces of the metal wiring and the surface modification layer.Type: GrantFiled: September 11, 2009Date of Patent: December 20, 2011Assignee: Renesas Electronics CorporationInventors: Makoto Ueki, Takahiro Onodera, Yoshihiro Hayashi
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Publication number: 20100096756Abstract: A semiconductor device has a multilayer interconnection including a copper interconnection film formed in a predetermined area within an insulating film, a liner film, and a high-melting-point metal film. The copper interconnection film is polycrystalline, and crystal grains occupying 40% or more of an area of a unit interconnection surface among crystal grains forming the polycrystal are oriented to (111) in a substrate thickness direction. The copper interconnection film has crystal conformity with the noble metal liner film. In a case where the high-melting-point metal film is formed of Ti and the noble metal liner film is a Ru film, the high-melting-point metal of Ti dissolves into Ru in a solid state to form the noble metal liner. Thus, a copper interconnection is formed with both of Cu diffusion barrier characteristics and Cu crystal conformity.Type: ApplicationFiled: January 8, 2008Publication date: April 22, 2010Inventors: Masayoshi Tagami, Yoshihiro Hayashi, Munehiro Tada, Takahiro Onodera, Naoya Furutake, Makoto Ueki, Mari Amano
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Publication number: 20100059887Abstract: Provided is a semiconductor device, which includes an interlayer insulating film formed on a semiconductor substrate, a wiring layer filled in a recess formed in the interlayer insulating film, and a cap insulating film. The interlayer insulating film includes a first SiOCH film and a surface modification layer including an SiOCH film formed by modifying a surface layer of the first SiOCH film, the SiOCH film having a lower carbon concentration and a higher oxygen concentration than the first SiOCH film has. The cap insulating film contacts with surfaces of the metal wiring and the surface modification layer.Type: ApplicationFiled: September 11, 2009Publication date: March 11, 2010Applicant: NEC ELECTRONICS CORPORATIONInventors: MAKOTO UEKI, TAKAHIRO ONODERA, YOSHIHIRO HAYASHI
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Image processing device and method for generating changes in the light and shade pattern of an image
Patent number: 6995869Abstract: In order to represent, as a video, changes in the light-and-shade patterns of an image with a reduced demand for storage capacity and a relatively small amount of preparation, light-and-shade pattern data representing the light-and-shade pattern to be added to an original image and constructed by assigning a palette number to each image region obtained by dividing the original image is prepared. A plurality of palette data constructed by assigning color information having brightness difference to each palette number are generated, the plurality of palette data being different from each other. A plurality of light-and-shade images each based on the light-and-shade pattern data and one of the palette data generated at the palette data generating step are translucently blended, in sequence, into the original image.Type: GrantFiled: October 4, 2001Date of Patent: February 7, 2006Assignees: Konami Corporation, Konami Computer Entertainment Tokyo, Inc.Inventor: Takahiro Onodera -
Patent number: 6861759Abstract: A semiconductor apparatus includes an under layer, a first insulating layer and a first conductive portion. The under layer is formed above a substrate. The first insulating layer is formed on the under layer. The first conductive portion is formed in a first concave portion which passes through the first insulating layer to the under layer. The first conductive portion includes a first barrier metal layer and a first metal portion. The first barrier metal layer is formed on a side wall and a bottom surface of the first concave portion. The first metal portion is formed on the first barrier metal layer such that the rest of the first concave portion is filled with the first metal portion. The first metal portion includes a first alloy including copper and aluminium.Type: GrantFiled: June 27, 2003Date of Patent: March 1, 2005Assignee: NEC Electronics CorporationInventors: Yoshihisa Matsubara, Masahiro Komuro, Manabu Iguchi, Takahiro Onodera, Norio Okada
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Publication number: 20040000719Abstract: A semiconductor apparatus includes an under layer, a first insulating layer and a first conductive portion. The under layer is formed above a substrate. The first insulating layer is formed on the under layer. The first conductive portion is formed in a first concave portion which passes through the first insulating layer to the under layer. The first conductive portion includes a first barrier metal layer and a first metal portion. The first barrier metal layer is formed on a side wall and a bottom surface of the first concave portion. The first metal portion is formed on the first barrier metal layer such that the rest of the first concave portion is filled with the first metal portion. The first metal portion includes a first alloy including copper and aluminium.Type: ApplicationFiled: June 27, 2003Publication date: January 1, 2004Applicant: NEC Electronics CorporationInventors: Yoshihisa Matsubara, Masahiro Komuro, Manabu Iguchi, Takahiro Onodera, Norio Okada
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Patent number: 6652354Abstract: In an apparatus for polishing a substrate, including a polishing platen for mounting the substrate thereon, a polishing head, a polishing pad adhered to a bottom face of the polishing head, and a rocking section for rocking. I.e., moving the polishing head in the horizontal direction with respect to the polishing platen, a control circuit controls a load of the polishing pad applied to the substrate in accordance with a contact area of the polishing pad to the substrate.Type: GrantFiled: May 9, 2001Date of Patent: November 25, 2003Assignees: NEC Corporation, Nikon CorporationInventors: Yoshihiro Hayashi, Takahiro Onodera, Yamato Samitsu, Kiyoshi Tanaka, Naoki Sasaki
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Patent number: 6425801Abstract: A polishing process monitoring apparatus of a semiconductor wafer is provided, which is capable of monitoring correctly the process independent of various factors affecting optical measurement, such as the configuration, material, and size of a layered structure on the wafer, and the geometric shapes of patterns and their arrangement for respective semiconductor chips.Type: GrantFiled: June 1, 1999Date of Patent: July 30, 2002Assignee: NEC CorporationInventors: Akira Takeishi, Hideo Mitsuhashi, Katsuhisa Ohkawa, Yoshihiro Hayashi, Takahiro Onodera
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Publication number: 20020041385Abstract: In order to represent, as a video, changes in the light-and-shade patterns of an image with a reduced demand for storage capacity and a relatively small amount of preparation, light-and-shade pattern data representing the light-and-shade pattern to be added to an original image and constructed by assigning a palette number to each image region obtained by dividing the original image is prepared. A plurality of palette data constructed by assigning color information having brightness difference to each palette number are generated, the plurality of palette data being different from each other. A plurality of light-and-shade images each based on the light-and-shade pattern data and one of the palette data generated at the palette data generating step are translucently blended, in sequence, into the original image.Type: ApplicationFiled: October 4, 2001Publication date: April 11, 2002Applicant: KONAMI CORPORATIONInventor: Takahiro Onodera
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Publication number: 20020037680Abstract: In an apparatus for polishing a substrate, including a polishing platen for mounting the substrate thereon, a polishing head, a polishing pad adhered to a bottom face of the polishing head, and a rocking section for rocking. I.e., moving the polishing head in the horizontal direction with respect to the polishing platen, a control circuit controls a load of the polishing pad applied to the substrate in accordance with a contact area of the polishing pad to the substrate.Type: ApplicationFiled: May 9, 2001Publication date: March 28, 2002Applicant: NEC CorporationInventors: Yoshihiro Hayashi, Takahiro Onodera, Yamato Samitsu, Kiyoshi Tanaka, Naoki Sasaki
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Patent number: 6270392Abstract: In an apparatus for polishing a substrate, including a polishing platen for mounting the substrate thereon, a polishing head, a polishing pad adhered to a bottom face of the polishing head, and a rocking section for rocking. I.e., moving the polishing head in the horizontal direction with respect to the polishing platen, a control circuit controls a load of the polishing pad applied to the substrate in accordance with a contact area of the polishing pad to the substrate.Type: GrantFiled: June 18, 1999Date of Patent: August 7, 2001Assignees: NEC Corporation, Niken CorporationInventors: Yoshihiro Hayashi, Takahiro Onodera, Yamato Samitsu, Kiyoshi Tanaka, Naoki Sasaki
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Patent number: 6165056Abstract: There is disclosed a polishing machine capable of flattening a wafer surface uniformly. The machine can modify the flatness of the surface during polishing. The machine has an index table and a polishing head 18. The table attracts the wafer to be polished such that the wafer faces upward. The table rotates to the primary polishing station. The polishing head has a pressure application cylinder 21 and a base plate 22. The cylinder is held to a carrier at a given angle. The base plate holds polishing cloth 24 and is mounted to the cylinder so as to be swingable in three dimensions. The cloth touches the wafer surface and rotates at a high speed, thus flattening it. At the second polishing station, polishing cloth attached to another polishing head touches the wafer surface and rotates at a high speed, thus finally polishing the wafer surface.Type: GrantFiled: December 2, 1998Date of Patent: December 26, 2000Assignees: NEC Corporation, Nikon CorporationInventors: Yoshihiro Hayashi, Takahiro Onodera, Kazuo Kobayashi
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Patent number: 5724057Abstract: The generation of flicker is prevented when the contrast of a displayed image is changed. The amplitude of the data voltage whose polarity is inverted at a timing synchronized with the display cycle of an image is changed based on the tone and the designed contrast. At the same time, the position (center) of 0 V relative to the amplitude of the data voltage is offset a larger amount as the contrast increases. This corrects a change V in voltage between the electrodes under the influence of the parasitic capacity of a TFT when the TFT is turned off, so that the voltage between the electrodes is also turned off despite the polarity of the data voltage applied to the liquid crystal, even when the designated contrast is relatively high and the amplitude of the data voltage is relatively small, and even when the designated contrast is relatively low and the amplitude of the data voltage is relatively large.Type: GrantFiled: November 7, 1994Date of Patent: March 3, 1998Assignee: International Business Machines CorporationInventors: Yasuhiro Kimura, Satoru Nishi, Takahiro Onodera
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Patent number: 5717251Abstract: After a pattern transfer of a first pattern image to a lower photo-sensitive layer of first material, a second pattern image is transferred to an upper photo-sensitive layer of second material higher in photo-sensitivity than the first material, and the first image and the second image are concurrently developed so as to form a composite etching mask through a simple process.Type: GrantFiled: August 5, 1996Date of Patent: February 10, 1998Assignee: NEC CorporationInventors: Yoshihiro Hayashi, Takahiro Onodera
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Patent number: 5640544Abstract: An object of the present invention is to provide a document data management system which can effect rapid screen display of document data. The document data management system comprises a communication processing apparatus for retrieving document data managed by another computer by way of a telecommunication line, a document data display apparatus for displaying on the screen document data requested by the user, a document data request processing apparatus for processing a document data retrieval request from the document data display apparatus, and a document data managing apparatus including document data writing controller which is utilized by the communication processing apparatus and document data reading controller which is utilized by the document data request processing apparatus.Type: GrantFiled: November 24, 1992Date of Patent: June 17, 1997Assignee: NEC CorporationInventors: Takahiro Onodera, Seiji Yamasuga