Abstract: A writing circuit includes storage to store writing data to be written to an OTP macro; a controller to apply a first signal that causes the OTP macro to execute writing of the writing data, and apply a second signal that causes the OTP macro to execute reading of data the OTP macro stores; and a comparator to compare the data read from the OTP macro in response to the second signal with the data stored in the storage and output a comparison result, wherein the controller ends a process associated with the writing data if the comparison result indicates a match, and applies the first and second signals again if the comparison result indicates a mismatch.

Abstract: A writing circuit includes storage to store writing data to be written to an OTP macro; a controller to apply a first signal that causes the OTP macro to execute writing of the writing data, and apply a second signal that causes the OTP macro to execute reading of data the OTP macro stores; and a comparator to compare the data read from the OTP macro in response to the second signal with the data stored in the storage and output a comparison result, wherein the controller ends a process associated with the writing data if the comparison result indicates a match, and applies the first and second signals again if the comparison result indicates a mismatch.

Abstract: A fault analysis apparatus includes: an extracting unit that extracts a segment including a point of fault from a plurality of paths in a target circuit; a detecting unit that detects a candidate path that extends, via the segment, from an upstream circuit element to a downstream circuit element; a judging unit that judges whether length of the candidate path is longer than a predetermined length; and a determining unit that determines whether to determine the candidate path as a target path to be subjected to a fault simulation based on a result of judgment.

Abstract: An integrated circuit includes a memory; a memory test circuit that tests the memory; and an input/output port, wherein the memory test circuit includes a latch circuit that outputs output of the memory, an address of the memory to be accessed is changed in accordance with a first clock signal, and output of the memory corresponding to the changed address is latched in accordance with a latch signal having a cycle of an integral multiple of the first clock signal, data of the latch circuit is output via the input/output port in a cycle of the latch signal, an address of a memory cell corresponding to the output of the memory to be latched by the latch circuit is changed, and the latch and the output is repeated.

Abstract: In a linear feedback shift register (LFSR), a four-bit shift register mainly using F/Fs is formed and an XOR circuit that feeds back an exclusive OR of a first bit and a last bit to the first bit is also provided, thereby outputting a test pattern having a maximum cycle of 15. A phase change circuit that can perform arbitrary phase change of a test pattern based on input of a control signal having a maximum clock number 4 and an average clock number log24 is also formed in the LFSR. As a result, a smaller clock count is required for the LFSR to output a test pattern that matches a test pattern automatically generated by an ATPG.

Abstract: A pattern correcting device corrects random test patterns generated by pseudo random number pattern generator (PRPG) into test patterns for a test to be input to shift registers. A pattern correcting device corrects the test patterns in unit of specified group, and individually releases correction of the test patterns when the correction in unit of the group is not appropriate. Furthermore, an unknown value mask device masks shift registers that output unknown values based on a control signal, and individually releases a mask of a shift register that outputs a fault value.

Abstract: A semiconductor integrated circuit includes plural shift registers that receive plural test patterns randomly generated, respectively, a mask device that masks, among the shift registers, a target shift register specified by a mask pattern randomly generated. When a shift register other than the target shift register outputs an unknown value, the mask device masks the shift register according to a control signal. When the target shift register outputs a fault value, the mask device releases a mask of the target shift register according to a control signal.

Abstract: An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.

Abstract: An integrated circuit includes a memory; a memory test circuit that tests the memory; and an input/output port, wherein the memory test circuit includes a latch circuit that outputs output of the memory, an address of the memory to be accessed is changed in accordance with a first clock signal, and output of the memory corresponding to the changed address is latched in accordance with a latch signal having a cycle of an integral multiple of the first clock signal, data of the latch circuit is output via the input/output port in a cycle of the latch signal, an address of a memory cell corresponding to the output of the memory to be latched by the latch circuit is changed, and the latch and the output is repeated.

Abstract: In a linear feedback shift register (LFSR), a four-bit shift register mainly using F/Fs is formed and an XOR circuit that feeds back an exclusive OR of a first bit and a last bit to the first bit is also provided, thereby outputting a test pattern having a maximum cycle of 15. A phase change circuit that can perform arbitrary phase change of a test pattern based on input of a control signal having a maximum clock number 4 and an average clock number log24 is also formed in the LFSR. As a result, a smaller clock count is required for the LFSR to output a test pattern that matches a test pattern automatically generated by an ATPG.

Abstract: An apparatus being able to not only detect a manufacturing defect of an integrated circuit but also specify a position at which the defect occurs even when outputs from scan paths are compressed and stored, or when the number of the scan paths is large. The apparatus has a pattern generator built in an integrated circuit to generate test patterns, a plurality of shift registers formed in parallel, into which the test patterns are shifted, and an output compressor for compressing a plurality of outputs shifted out from the shift registers with check bits of a Hamming code, and outputting them to the outside of the integrated circuit.

Abstract: A pattern correcting device corrects random test patterns generated by pseudo random number pattern generator (PRPG) into test patterns for a test to be input to shift registers. A pattern correcting device corrects the test patterns in unit of specified group, and individually releases correction of the test patterns when the correction in unit of the group is not appropriate. Furthermore, an unknown value mask device masks shift registers that output unknown values based on a control signal, and individually releases a mask of a shift register that outputs a fault value.

Abstract: A semiconductor integrated circuit includes plural shift registers that receive plural test patterns randomly generated, respectively, a mask device that masks, among the shift registers, a target shift register specified by a mask pattern randomly generated. When a shift register other than the target shift register outputs an unknown value, the mask device masks the shift register according to a control signal. When the target shift register outputs a fault value, the mask device releases a mask of the target shift register according to a control signal.

Abstract: A fault analysis apparatus includes: an extracting unit that extracts a segment including a point of fault from a plurality of paths in a target circuit; a detecting unit that detects a candidate path that extends, via the segment, from an upstream circuit element to a downstream circuit element; a judging unit that judges whether length of the candidate path is longer than a predetermined length; and a determining unit that determines whether to determine the candidate path as a target path to be subjected to a fault simulation based on a result of judgment.

Abstract: The present invention provides an integrated circuit test device and method which creates a pattern for minimizing a difference from a pattern generated by a pattern generation device. In the invention, a list of all failures assumed to be in the circuit is created, and, for example, a random number pattern is inputted so that a signal value in the circuit is defined by a logic simulation using the inputted pattern, as a result of which the controllability, observability and testability are calculated. A target failure minimizing the testability is selected from the list, for which target failure path-sensitization is performed using the controllability and observability of the input pattern, which pattern is corrected so as to minimize the number of inversions of signal values of the input pattern. A failure simulation for the target failure is also performed using the corrected pattern, and when a failure to be detected further exists, the failure is removed from the failure list.

Abstract: An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.

Abstract: An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.

Abstract: The present invention provides an integrated circuit test device and method which creates a pattern for minimizing a difference from a pattern generated by a pattern generation device. In the invention, a list of all failures assumed to be in the circuit is created, and, for example, a random number pattern is inputted so that a signal value in the circuit is defined by a logic simulation using the inputted pattern, as a result of which the controllability, observability and testability are calculated. A target failure minimizing the testability is selected from the list, for which target failure path-sensitization is performed using the controllability and observability of the input pattern, which pattern is corrected so as to minimize the number of inversions of signal values of the input pattern. A failure simulation for the target failure is also performed using the corrected pattern, and when a failure to be detected further exists, the failure is removed from the failure list.

Abstract: An apparatus being able to not only detect a manufacturing defect of an integrated circuit but also specify a position at which the detect occurs even when outputs from scan paths are compressed and stored, or when the number of the scan paths is large. The apparatus has a pattern generator built in an integrated circuit to generate test patterns, a plurality of shift registers formed in parallel, into which the test patterns are shifted, and an output compressor for compressing a plurality of outputs shifted out from the shift registers with check bits of a Hamming code, and outputting them to the outside of the integrated circuit.

Abstract: An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus comprises a pattern generator built in an integrated circuit to generate a test pattern, a plurality of shift registers configured with sequential circuit elements F/Fs inside the integrated circuit, and a pattern modifier modifying the test pattern generated by the pattern generator according to an external input, and inputting it to the plural shift registers. The apparatus is used as a testing apparatus for detecting manufacturing failure of an integrated circuit such as an LSI (Large Scale Integration) or the like.