Patents by Inventor Takahisa Kanemura
Takahisa Kanemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240008278Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: July 26, 2023Publication date: January 4, 2024Applicant: KIOXIA CORPORATIONInventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
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Patent number: 11849586Abstract: A semiconductor device is provided, including: a substrate; a first stacked portion including a plurality of first electrode layers stacked in a first direction via a first insulator; a second stacked portion provided above the first stacked portion and including a plurality of second electrode layers stacked in the first direction via a second insulator; a connection portion provided between the first stacked portion and the second stacked portion, and including a third insulator; a column-shaped portion extending in the first stacked portion, the second stacked portion, and the connection portion in the first direction, and including a semiconductor body and a charge storage portion; and a semiconductor pillar provided between the substrate and the column-shaped portion, and in contact with the substrate and the semiconductor body of the column-shaped portion.Type: GrantFiled: October 3, 2022Date of Patent: December 19, 2023Assignee: Kioxia CorporationInventors: Kaito Shirai, Hideto Takekida, Tatsuo Izumi, Reiko Shamoto, Takahisa Kanemura, Shigeo Kondo
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Patent number: 11784231Abstract: According to one embodiment, a semiconductor device includes a memory region and a peripheral circuit region, the peripheral circuit region includes a first region and a second region outside of the first region. The semiconductor device includes, in the first region, a transistor including a gate insulating layer and a gate structure that includes a gate electrode. A first structure is in the second region and includes a first insulating layer and a dummy gate electrode on the first insulating layer. The first insulating layer has a side surface facing outward from the peripheral circuit region and a second insulating layer that covers the first side surface and is an insulating material other than a silicon oxide.Type: GrantFiled: August 28, 2020Date of Patent: October 10, 2023Assignee: Kioxia CorporationInventor: Takahisa Kanemura
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Patent number: 11751399Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: GrantFiled: April 8, 2022Date of Patent: September 5, 2023Assignee: KIOXIA CORPORATIONInventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
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Publication number: 20230027173Abstract: A semiconductor device is provided, including: a substrate; a first stacked portion including a plurality of first electrode layers stacked in a first direction via a first insulator; a second stacked portion provided above the first stacked portion and including a plurality of second electrode layers stacked in the first direction via a second insulator; a connection portion provided between the first stacked portion and the second stacked portion, and including a third insulator; a column-shaped portion extending in the first stacked portion, the second stacked portion, and the connection portion in the first direction, and including a semiconductor body and a charge storage portion; and a semiconductor pillar provided between the substrate and the column-shaped portion, and in contact with the substrate and the semiconductor body of the column-shaped portion.Type: ApplicationFiled: October 3, 2022Publication date: January 26, 2023Applicant: Kioxia CorporationInventors: Kaito SHIRAI, Hideto TAKEKIDA, Tatsuo IZUMI, Reiko SHAMOTO, Takahisa KANEMURA, Shigeo KONDO
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Patent number: 11502100Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.Type: GrantFiled: September 3, 2020Date of Patent: November 15, 2022Assignee: Kioxia CorporationInventors: Kaito Shirai, Hideto Takekida, Tatsuo Izumi, Reiko Shamoto, Takahisa Kanemura, Shigeo Kondo
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Publication number: 20220231032Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: April 8, 2022Publication date: July 21, 2022Applicant: KIOXIA CORPORATIONInventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
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Patent number: 11329060Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: GrantFiled: September 22, 2020Date of Patent: May 10, 2022Assignee: KIOXIA CORPORATIONInventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
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Publication number: 20210296457Abstract: According to one embodiment, a semiconductor device includes a memory region and a peripheral circuit region, the peripheral circuit region includes a first region and a second region outside of the first region. The semiconductor device includes, in the first region, a transistor including a gate insulating layer and a gate structure that includes a gate electrode. A first structure is in the second region and includes a first insulating layer and a dummy gate electrode on the first insulating layer. The first insulating layer has a side surface facing outward from the peripheral circuit region and a second insulating layer that covers the first side surface and is an insulating material other than a silicon oxide.Type: ApplicationFiled: August 28, 2020Publication date: September 23, 2021Inventor: Takahisa KANEMURA
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Patent number: 10930660Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: GrantFiled: February 18, 2020Date of Patent: February 23, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
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Publication number: 20210005616Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: September 22, 2020Publication date: January 7, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
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Publication number: 20200403000Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.Type: ApplicationFiled: September 3, 2020Publication date: December 24, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Kaito SHIRAI, Hideto Takekida, Tatsuo Izumi, Reiko Shamoto, Takahisa Kanemura, Shigeo Kondo
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Patent number: 10804290Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.Type: GrantFiled: March 13, 2019Date of Patent: October 13, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kaito Shirai, Hideto Takekida, Tatsuo Izumi, Reiko Shamoto, Takahisa Kanemura, Shigeo Kondo
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Publication number: 20200185395Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: February 18, 2020Publication date: June 11, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
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Patent number: 10608007Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: GrantFiled: July 15, 2019Date of Patent: March 31, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
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Publication number: 20190341391Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: July 15, 2019Publication date: November 7, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
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Patent number: 10431590Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: GrantFiled: January 5, 2018Date of Patent: October 1, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
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Publication number: 20190214405Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.Type: ApplicationFiled: March 13, 2019Publication date: July 11, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Kaito SHIRAI, Hideto Takekida, Tatsuo Izumi, Reiko Shamoto, Takahisa Kanemura, Shigeo Kondo
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Publication number: 20190013355Abstract: According to one embodiment, the first lines extend in a first direction. The first gate electrodes extend in a second direction intersecting with the first direction. The second lines extend in a third direction orthogonal to the first direction and the second direction. The semiconductor portion is disposed between the first gate electrodes, and between one of the first lines and one of the second lines, and connected to the first line and the second line. The semiconductor portion has a column shape. The semiconductor portion includes a plurality of channels isolated in a direction orthogonal to the third direction. The second gate electrode is provided between the channels. The insulating film is provided between the semiconductor portion and the first gate electrode, and between the semiconductor portion and the second gate electrode.Type: ApplicationFiled: February 27, 2018Publication date: January 10, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hikari TAJIMA, Takashi IZUMIDA, Takahisa KANEMURA, Hiroki TOKUHIRA
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Patent number: 9985044Abstract: A semiconductor memory device according to an embodiment, includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: GrantFiled: September 14, 2016Date of Patent: May 29, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku