Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array that includes a plurality of memory cells.

Abstract: A semiconductor memory device according to an embodiment, includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array that includes a plurality of memory cells.

Abstract: According to one embodiment, a solid-state imaging device includes a plurality of photoelectric conversion elements, a field effect transistor, a trench, and a P-type impurity diffusion region. The plurality of photoelectric conversion elements is two-dimensionally arranged in a semiconductor layer. The field effect transistor includes N-type source and drain on a surface side of the semiconductor layer. The trench penetrates through a surface and a rear surface of the semiconductor layer and surrounds each of the photoelectric conversion elements. The width of the trench is enlarged from the surface of the semiconductor layer toward a position at a predetermined depth, and is not enlarged at a position deeper than the position at the predetermined depth. The P-type impurity diffusion region is arranged in a side surface of the trench.

Abstract: An integrated circuit device according to an embodiment includes a semiconductor substrate, a first semiconductor member and a second semiconductor member provided on the semiconductor substrate, a first electrode disposed between the first semiconductor member and the second semiconductor member, and a second electrode disposed between the semiconductor substrate and the first electrode. The first semiconductor member and the second semiconductor member extend in a first direction perpendicular to an upper surface of the semiconductor substrate. The first semiconductor member and the second semiconductor member are separated in a second direction orthogonal to the first direction. The first electrode extends in a third direction intersecting both the first direction and the second direction. The second electrode extends in the third direction.

Abstract: A semiconductor device according to an embodiment comprises: a gate insulating film formed on a semiconductor substrate; a semiconductor layer formed on the gate insulating film; and a first metal layer formed to be electrically connected to the semiconductor layer. 1×1019 atoms/cm3 or more of a Group VI element exists in an interface of the semiconductor layer and the first metal layer.

Abstract: An integrated circuit device according to an embodiment includes a semiconductor substrate, a first semiconductor member and a second semiconductor member provided on the semiconductor substrate, a first electrode disposed between the first semiconductor member and the second semiconductor member, and a second electrode disposed between the semiconductor substrate and the first electrode. The first semiconductor member and the second semiconductor member extend in a first direction perpendicular to an upper surface of the semiconductor substrate. The first semiconductor member and the second semiconductor member are separated in a second direction orthogonal to the first direction. The first electrode extends in a third direction intersecting both the first direction and the second direction. The second electrode extends in the third direction.

Abstract: In one embodiment, a semiconductor device includes a substrate, and a source region of a first conductivity type disposed on a surface of the substrate. The device further includes a tunnel insulator disposed on the source region, and an impurity semiconductor layer of a second conductivity type disposed on the tunnel insulator, the second conductivity type being different from the first conductivity type. The device further includes a gate insulator disposed on the impurity semiconductor layer, and a gate electrode disposed on the gate insulator. The device further includes a drain region of the second conductivity type disposed on the substrate so as to be separated from the impurity semiconductor layer, or disposed on the substrate as a portion of the impurity semiconductor layer.

Abstract: In one embodiment, a semiconductor device includes a substrate, and a source region of a first conductivity type disposed on a surface of the substrate. The device further includes a tunnel insulator disposed on the source region, and an impurity semiconductor layer of a second conductivity type disposed on the tunnel insulator, the second conductivity type being different from the first conductivity type. The device further includes a gate insulator disposed on the impurity semiconductor layer, and a gate electrode disposed on the gate insulator. The device further includes a drain region of the second conductivity type disposed on the substrate so as to be separated from the impurity semiconductor layer, or disposed on the substrate as a portion of the impurity semiconductor layer.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

Abstract: A semiconductor memory device according to an embodiment of the present invention includes a substrate, a first gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the first gate insulator, a second gate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the second gate insulator, an intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the intergate insulator, at least one of the first and second floating gates including a metal layer.

Abstract: A semiconductor device of an example of the invention comprises a memory cell and a select gate transistor provided for the memory cell. A gate electrode of the select gate transistor has a Tri-gate structure in which an upper surface of a gate insulating film formed above a channel of the select gate transistor is set higher than a portion of an upper surface of an element isolation region of the select gate transistor.

Abstract: A semiconductor storage device has a semiconductor substrate, a plurality of first insulating films formed on the semiconductor substrate with predetermined spacing therebetween, an element isolation region formed between the first insulating films in a first direction, a floating gate electrode comprising a first charge accumulation film formed on the first insulating film, a second charge accumulation film formed on the first charge accumulation film and having a width in a second direction orthogonal to the first direction smaller than the width of the first charge accumulation film, and a third charge accumulation film formed on the second charge accumulation film and having the width in the second direction larger than the width of the second charge accumulation film, a second insulating film formed on the second charge accumulation film and between the second charge accumulation film and the element isolation region, a third insulating film formed on the charge accumulation film and the element isolatio

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

Abstract: In one embodiment, there is provided an ion implanting simulating method of implanting incident particles into a substrate, and gaining stationary position coordinates of each of the incident particles in the substrate, thereby calculating the distribution of the incident particles in the substrate. In the method, the followings are repeated desired times by a computer: implanting one of the incident particles into the substrate; calculating the trace of the incident particle traveling in the substrate while undergoing collision with an atom contained in the substrate repeatedly, and the energy lost from the incident particle by the collision, based on a beforehand-inputted composition of the substrate, thereby calculating stationary position coordinates of the incident particle; and renewing the composition of the substrate in accordance with a matter that the substrate contains the implanted incident particle.

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

Abstract: A process simulation method includes: converting condition data of plasma doping for introducing an impurity into a semiconductor in a plasma atmosphere to corresponding condition data of ion implantation for implanting impurities as an ion beam into the semiconductor; and calculating device structure data on the basis of the ion implantation condition data converted from the plasma doping condition data.

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.