Patents by Inventor Takahisa Suzuki

Takahisa Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170094579
    Abstract: A sensor network system includes: a plurality of sensor nodes; and a server configured to collect data from the plurality of sensor nodes. When a first sensor node among the plurality of sensor nodes obtains data, the first sensor node selects a first transmission mode to directly transmit the data to the server or a second transmission mode to transmit the data to another sensor node among the plurality of sensor nodes based on a first energy to directly transmit the data to the server, a second energy to transmit the data to the other sensor node, and a third energy to store the data in the first sensor node, and the first sensor node transmits the data to the server or the other sensor node in the selected transmission mode.
    Type: Application
    Filed: December 13, 2016
    Publication date: March 30, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Koji Kurihara, Koichiro Yamashita, Takahisa Suzuki, Toshiya Otomo
  • Patent number: 9563465
    Abstract: A multi-task scheduling method includes assigning a first thread to a first processor; detecting a second thread that is executed after the first thread; calculating based on a load of a processor that is assigned a third thread that generates the second thread, a first time that lasts until a start of the second thread; calculating a second time that lasts until completion of execution of the first thread; and changing a first time slice of the first processor to a second time slice when the second time is greater than the first time.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: February 7, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki
  • Patent number: 9565049
    Abstract: A communication apparatus includes a processor configured to access memory of the communication apparatus; communicate with a second apparatus; detect an access request generated by the communication apparatus; determine whether an address of access targeted data indicated in the detected access request is an address allocated to the memory of the communication apparatus; and perform control for selecting and executing based on a determination result, any one among a process of accessing the memory of the communication apparatus based on the access request and a process of communicating with the second apparatus based on the access request.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: February 7, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara
  • Patent number: 9558152
    Abstract: A synchronization method is executed by a multi-core processor system. The synchronization method includes registering based on a synchronous command issued from a first CPU, CPUs to be synchronized and a count of the CPUs into a specific table; counting by each of the CPUs and based on a synchronous signal from the first CPU, an arrival count for a synchronous point, and creating by each of the CPUs, a second shared memory area that is a duplication of a first shared memory area accessed by processes executed by the CPUs; and comparing the first shared memory area and the second shared memory area when the arrival count becomes equal to the count of the CPUs, and based on a result of the comparison, judging the processes executed by the CPUs.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: January 31, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Koichiro Yamashita, Hiromasa Yamauchi, Takahisa Suzuki, Koji Kurihara
  • Patent number: 9547576
    Abstract: A multi-core processor system includes a multi-core processor that has plural core groups; and a storage device that stores a constraint on execution time for each application. A first identified core of the multi-core processor is configured to identify a constraint on execution time of a given application that is among the applications and for which an invocation instruction is received; determine whether the identified constraint meets a performance drop condition; assign the given application to a predetermined core of the multi-core processor, upon determining that the identified constraint meets the performance drop condition; and notify a second identified core of a core group among the core groups, of an assignment instruction for the given application, upon determining that the identified constraint does not meet the performance drop condition.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: January 17, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Toshiya Otomo
  • Patent number: 9549412
    Abstract: A scheduling method is executed by a first apparatus among a plurality of apparatuses. The scheduling method includes assigning a process to at least one apparatus among the apparatuses based on a first table that includes each communication strength of the apparatuses; receiving an execution result of the process and a communication strength from the at least one apparatus; and creating the first table based on the received communication strength.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: January 17, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Toshiya Otomo, Naoki Odate
  • Patent number: 9529073
    Abstract: A determining method executed by a processor includes obtaining distance information that indicates a distance between monitoring apparatuses disposed to encompass a given area in which wireless communications apparatuses are scattered; causing a wireless signal to be transmitted and received between the monitoring apparatuses by multi-hop communication among the wireless communications apparatuses; calculating an estimated distance between the monitoring apparatuses, based on a hop count of the wireless signal multi-hop communicated among the monitoring apparatuses; and making a determination concerning a vacant area in which none of the wireless communications apparatuses is present, based on a result of comparison of the distance indicated by the obtained distance information and the calculated estimated distance.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: December 27, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Toshiya Otomo, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Koji Kurihara, Yuta Teranishi
  • Patent number: 9529549
    Abstract: A data processing method that is executed by a first data processing apparatus included among plural data processing apparatuses, includes producing a copy of data, and restoration information that includes a first address of memory to which the copy of the data is stored; transmitting any one among the data and the copy of the data to a second data processing apparatus that is included among the data processing apparatuses; and storing the restoration information to shared memory that is memory of at least one data processing apparatus among the data processing apparatuses, and shared among the data processing apparatuses.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: December 27, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Toshiya Otomo, Koichiro Yamashita, Naoki Odate, Takahisa Suzuki, Hiromasa Yamauchi, Koji Kurihara
  • Publication number: 20160357604
    Abstract: A data processing system includes an interrupt controller that counts, as an interrupt processing execution count, executions of interrupt processing by threads executed by data processing devices; and a processor that is configured to select one scheduling method from among a plurality of scheduling methods, based on the interrupt processing execution count.
    Type: Application
    Filed: August 17, 2016
    Publication date: December 8, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Koji KURIHARA, Koichiro YAMASHITA, Takahisa SUZUKI, Hiromasa YAMAUCHI, Toshiya OTOMO, Naoki ODATE
  • Patent number: 9513965
    Abstract: A data processing system includes an interrupt controller that counts, as an interrupt processing execution count, executions of interrupt processing by threads executed by data processing devices; and a processor that is configured to select one scheduling method from among a plurality of scheduling methods, based on the interrupt processing execution count.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: December 6, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Koji Kurihara, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Toshiya Otomo, Naoki Odate
  • Patent number: 9515917
    Abstract: A given sensor node, upon determining that data processing requested by another sensor node cannot be completed by the given sensor node, selects a sensor node that based on hop count based information stored in a storage apparatus, is away from a receiver. The given sensor node transmits to the selected sensor node, request notification requesting execution of the data processing exclusive of an executable portion. The given sensor node executes the executable portion, upon receiving securement completion notification indicating that the execution of the data processing indicated in the transmitted request notification can be completed by at least one sensor node among plural sensor nodes.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: December 6, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Koji Kurihara, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Yuta Teranishi
  • Patent number: 9507633
    Abstract: A scheduling method that is executed by a first central processing unit (CPU) includes determining whether a task belongs to a first task category; determining whether a first access area accessed by the task is located in a first memory or a second memory, when the task belongs to the first task category; and setting a memory accessed by the task to the first memory or the second memory, based on a result at the determining.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: November 29, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Koji Kurihara, Koichiro Yamashita, Takahisa Suzuki, Naoki Odate, Toshiya Otomo
  • Patent number: 9507645
    Abstract: A thread processing method that is executed by a multi-core processor, includes supplying a command to execute a first thread to a first processor; judging a dependence relationship between the first thread and a second thread to be executed by a second processor; comparing a first threshold and a frequency of access of any one among shared memory and shared cache memory by the first thread; and changing a phase of a first operation clock of the first processor when the access frequency is greater than the first threshold and upon judging that no dependence relationship exists.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: November 29, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Toshiya Otomo, Naoki Odate
  • Patent number: 9507635
    Abstract: A scheduling method is executed by a given CPU among multiple CPUs. The scheduling method includes subtracting for each of the CPUs, a number of processes assigned to the CPU from a maximum number of speculative processes that can be assigned to each of the CPUs; summing results yielded at the subtracting to yield a total number of speculative processes; and assigning to the CPUs, speculative processes of a number is less than or equal to the total number of speculative processes.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 29, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Toshiya Otomo, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Koji Kurihara, Naoki Odate
  • Patent number: 9503386
    Abstract: A computer-readable recording medium stores a data sharing program that causes a processor of a first terminal to execute a process that includes detecting a communication bandwidth used between the first terminal and a second terminal that are communicably connected in an ad-hoc network; comparing the detected communication bandwidth and a bandwidth related to a storage apparatus of the first terminal; determining an operation scheme related to data sharing of data in the storage apparatus of the first terminal and data in a storage apparatus of the second terminal, based on a comparison result obtained at the comparing; notifying the second terminal of the determined operation scheme; and executing a mounting process that enables access of the storage apparatus of the first terminal by the second terminal, based on the determined operation scheme.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 22, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Koji Kurihara, Koichiro Yamashita, Hiromasa Yamauchi, Takahisa Suzuki
  • Publication number: 20160334854
    Abstract: A scheduling method is executed by a processor, and includes detecting a transition from a first process to a second process; acquiring from memory, an operating frequency and a CPU count for executing the second process; suspending a CPU under operation or starting a suspended CPU, based on the CPU count; and assigning the operating frequency to a CPU that is to execute the second process.
    Type: Application
    Filed: July 26, 2016
    Publication date: November 17, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Takahisa SUZUKI, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara, Toshiya Otomo, Naoki ODATE, Tetsuo HIRAKI
  • Patent number: 9483101
    Abstract: A multicore processor system includes multiple processors; a device; a memory that stores information of voltage and clock frequency for minimizing power consumption in connection with a number of the processors accessing to the device; and a power control unit that controls the voltage and the clock frequency of the processors on the basis of the information stored in the memory if the number of the processors accessing to the device changes.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: November 1, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Takahisa Suzuki, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki, Toshiya Otomo
  • Publication number: 20160316443
    Abstract: Among plural communications nodes that transfer data to a communications apparatus by multihop communication, a communications node includes a transmitting circuit configured to transmit a synchronization request signal requesting transmission of a synchronization signal for synchronizing the multihop communication at the communications node; a receiving circuit configured to receive the synchronization signal in response to the synchronization request signal transmitted by the transmitting circuit; and a power control circuit configured to control the receiving circuit such that a state of the receiving circuit is a first state where power consumption of the receiving circuit is a first power before the transmitting circuit transmits the synchronization request signal and is a second state where the power consumption of the receiving circuit is a second power that is higher than the first power after the transmitting circuit transmits the synchronization request signal.
    Type: Application
    Filed: July 7, 2016
    Publication date: October 27, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Toshiya Otomo, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi
  • Publication number: 20160308731
    Abstract: An analysis method includes detecting, by a computer, a malfunctioning node count of nodes malfunctioning among plural nodes in a period during operation of a system configured to realize a function even when a portion of nodes malfunction among the plural nodes; and calculating, by the computer and based on the detected malfunctioning node count and the period, a count of nodes that malfunction per unit time after the period.
    Type: Application
    Filed: June 28, 2016
    Publication date: October 20, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Toshiya Otomo
  • Patent number: 9471123
    Abstract: A power supply control method includes detecting that a result of a first function performed by a first device ceases to be displayed on a display screen; suspending power supply to the first device and supplying power to a second device, based on a detection of the result ceasing to be displayed; and causing the second device to output a response signal to a CPU in response to a control signal from the CPU.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: October 18, 2016
    Assignee: Fujitsu Limited
    Inventors: Tetsuo Hiraki, Hiromasa Yamauchi, Koichiro Yamashita, Fumihiko Hayakawa, Naoki Odate, Takahisa Suzuki, Koji Kurihara