Patents by Inventor Takahisa Suzuki

Takahisa Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9164823
    Abstract: An access method is executed by a multi-core processor system. The access method includes activating a driver that corresponds to a first CPU, based on a start of execution of a first application; starting measurement of an access time period, based on access of a peripheral device; outputting, when the access time period exceeds a predetermined time period, a detection signal to reset the driver; and prohibiting, when the access time period exceeds a predetermined time period, writing into a register retaining data to be written into the peripheral device from the first CPU.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: October 20, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Koichiro Yamashita, Hiromasa Yamauchi, Takahisa Suzuki, Koji Kurihara, Fumihiko Hayakawa
  • Publication number: 20150289192
    Abstract: When a first sensor node has a large power consumption, an information processing apparatus propagates a portion of request information for a data process having the request recipient set to a second sensor node, through a path that does not pass through the first sensor node. For example, the information processing apparatus changes a division rate at a third sensor node acting as a branching point for the request information for the data process having the request recipient set to the second sensor node to thereby change the distribution of the transferred data amount and equalize the power consumption of the sensor nodes in a sensor network.
    Type: Application
    Filed: June 22, 2015
    Publication date: October 8, 2015
    Applicant: Fujitsu Limited
    Inventors: Takahisa SUZUKI, Koichiro YAMASHITA, Hiromasa YAMAUCHI, Toshiya OTOMO
  • Publication number: 20150271058
    Abstract: A given sensor node, upon determining that data processing requested by another sensor node cannot be completed by the given sensor node, selects a sensor node that based on hop count based information stored in a storage apparatus, is away from a receiver. The given sensor node transmits to the selected sensor node, request notification requesting execution of the data processing exclusive of an executable portion. The given sensor node executes the executable portion, upon receiving securement completion notification indicating that the execution of the data processing indicated in the transmitted request notification can be completed by at least one sensor node among plural sensor nodes.
    Type: Application
    Filed: June 5, 2015
    Publication date: September 24, 2015
    Inventors: Koji KURIHARA, Koichiro YAMASHITA, Takahisa SUZUKI, Hiromasa YAMAUCHI, Yuta TERANISHI
  • Publication number: 20150244603
    Abstract: A computer obtains first information related to a first communication path that is from a first aggregating apparatus to a second aggregating apparatus when the second aggregating apparatus receives a transmission signal that is from sensor nodes in response to a transmission instruction that is transmitted by the first aggregating apparatus and propagated by multi-hop communication via the sensor nodes. The computer obtains from a storage apparatus, second information that is related to a second communication path that is a stationary path from the first aggregating apparatus to reception by the second aggregating apparatus. The computer determines correspondence of the first communication path and the second communication path by comparison of the first information and the second information, and if the first communication path and the second communication path do not correspond, the computer determines that an abnormality related to a sensor node is present.
    Type: Application
    Filed: May 8, 2015
    Publication date: August 27, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Koichiro YAMASHITA, Takahisa SUZUKI, Hiromasa YAMAUCHI, Toshiya OTOMO
  • Publication number: 20150242317
    Abstract: A multi-core processor system includes a memory unit that for each input destination thread defined as a thread to which given data is input, stores identification information of an assignment destination core for the input destination thread; and a multi-core processor that is configured to update, in the memory unit and when assignment of the input destination thread to a multi-core processor is detected, the identification information of the assignment destination core for the input destination thread; detect a writing request for the given data; identify based on the given data for which the writing request is detected, the updated identification information among information stored in the memory unit; and store the given data to a memory of the assignment destination core that is indicated in the updated identification information and among cores making up the multi-core processor.
    Type: Application
    Filed: May 12, 2015
    Publication date: August 27, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Takahisa SUZUKI, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara
  • Publication number: 20150238069
    Abstract: An endoscope which promotes downsizing and cost reduction, and a manufacturing method of an endoscope are provided. For this reason, in an endoscope, a lens unit containing a lens in a lens tube, an image capturing element of which an image capturing surface is covered with element cover glass, and an adhesive resin fixing the lens unit of which an optical axis of the lens is coincident with the center of the image capturing surface to the element cover glass with a separation portion are disposed.
    Type: Application
    Filed: February 18, 2015
    Publication date: August 27, 2015
    Inventors: Akinori Osada, Takafumi Sanada, Yasuyuki Hanada, Naoyuki Haraguchi, Takahisa Suzuki, Tooru Tanaka, Hiroshi Nagayasu
  • Patent number: 9110886
    Abstract: A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: August 18, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara
  • Publication number: 20150227400
    Abstract: A converting apparatus includes a storage configured to store correspondence information that indicates correspondence relations between logical addresses accessed by a processor for booting and physical addresses converted from the logical addresses, the correspondence information being correlated with each type of an event booting the processor; and an address converter configured to select correspondence information related to the type of the event, specify a physical address converted from the logical address accessed by the processor in case of the processor accessing a logical address in response to the event, and control the processor to get a program stored in the storage, the program indicated by the specified physical address.
    Type: Application
    Filed: March 26, 2015
    Publication date: August 13, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Koichiro YAMASHITA, Hiromasa YAMAUCHI, Takahisa SUZUKI, Koji KURIHARA, Toshiya OTOMO
  • Publication number: 20150229705
    Abstract: A communications apparatus includes a receiving circuit that, when sending a startup instruction to start up another communications apparatus within a communication area, receives from the other communications apparatus, information indicating a period required for startup of the other communications apparatus; a processor that stores to a storage device, a standby period based on the period indicated by the information received by the receiving circuit; a communications circuit that sends the startup instruction within the communication area; and a timer that detects that the standby period stored in the storage device by the processor has elapsed after sending of the startup instruction from the communications circuit. The communications circuit sends data within the communication area when the timer detects that the standby period has elapsed.
    Type: Application
    Filed: March 26, 2015
    Publication date: August 13, 2015
    Applicant: Fujitsu Limited
    Inventors: Takahisa SUZUKI, Koichiro Yamashita, Hiromasa Yamauchi, Toshiya Otomo
  • Patent number: 9098414
    Abstract: A multi-core processor system includes shared memory shared by cores of a multi-core processor; first cache memories respectively for each of the cores; a second cache memory between the shared memory and the first cache memories, and storing shared data shared by the cores and referred to by at least threads executed by the multi-core processor; a reading unit that reads a value of a given variable from the shared memory; a determining unit that based on a read request for the given variable, determines whether the given variable is shared data or non-shared data that is referred to by only one thread; and a transferring unit that, when the given variable is determined as non-shared data, transfers without using the second cache memory, the value of the given variable to a first cache memory of a core that is a request origin of the read request.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: August 4, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Takahisa Suzuki, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara
  • Publication number: 20150211846
    Abstract: An event location analysis system includes a first wireless terminal device. The first wireless terminal device includes a first measurement unit, a second measurement unit, and a first processor. The second measurement unit consumes larger amounts of power than the first measurement unit consumes. The first processor is configured to transmit a first notification signal upon detecting a first event on basis of a measurement value of the first measurement unit. The first processor is configured to start the second measurement unit upon receiving a second notification signal. The first processor is configured to activate a measurement operation of the first measurement unit and a measurement operation of the second measurement unit after the second measurement unit is started. The first processor is configured to stop the measurement operation of the second measurement unit after a predetermined time has elapsed since the start of the second measurement unit.
    Type: Application
    Filed: November 21, 2014
    Publication date: July 30, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Takahisa SUZUKI, Koichiro Yamashita, Koji Kurihara, Toshiya Otomo
  • Patent number: 9092255
    Abstract: A multi-core processor system includes a given configured to queue an interrupt process of a software interrupt request to the given core, and execute queued processes in the order of queuing at the given core; execute preferentially an interrupt process of a hardware interrupt request to the given core over a process under execution at the given core; determine whether the software interrupt request is a specific software interrupt request; and perform control to preferentially execute the interrupt process without queuing, upon determining that the software interrupt request is the specific software interrupt request.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: July 28, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara
  • Publication number: 20150201362
    Abstract: A communications apparatus includes a reception signal processor that receives a wireless signal; a processor that controls a wait time that the reception signal processor waits for reception of wireless signals that include data to be transmitted and information of transmission paths; extracts from the information of the transmission paths included in the wireless signals received by the reception signal processor during the wait time, information of a common relay point in the transmission paths; determines a network state according to a ratio of transmission paths that include the common relay point, among a total count of the transmission paths; and generates based on the determined network state, a signal that includes information of a relay point; and a transmission signal processor that transmits the generated signal.
    Type: Application
    Filed: March 25, 2015
    Publication date: July 16, 2015
    Applicant: Fujitsu Limited
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Toshiya Otomo
  • Publication number: 20150201396
    Abstract: A communications apparatus is included among a communications apparatus group arranged in a given area and capable of communicating with a nearby communications apparatus. The communications apparatus includes a sensor that detects a given property at a location of the communications apparatus; communications circuitry that receives from the nearby communications apparatus, a detection result that is obtained by another communications apparatus, for the given property at the location of the other communications apparatus; a processor that determines whether a difference between the detection result received by the communications circuitry and a detection result of the sensor is a given amount or less.
    Type: Application
    Filed: March 26, 2015
    Publication date: July 16, 2015
    Applicant: Fujitsu Limited
    Inventors: Koichiro YAMASHITA, Hiromasa Yamauchi, Takahisa Suzuki, Koji Kurihara, Toshiya Otomo
  • Patent number: 9069756
    Abstract: A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: June 30, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara
  • Publication number: 20150177361
    Abstract: A determining method includes obtaining by each monitoring apparatus among plural monitoring apparatuses disposed encompassing a given area having plural wireless communications apparatuses, hop count information that indicates a hop count of a wireless signal transmitted by one wireless communications apparatus among the wireless communications apparatuses and received by the monitoring apparatus via multi-hop communication by the wireless communications apparatuses; calculating by each monitoring apparatus, an estimated line that represents candidates of a position of the one wireless communications apparatus, the estimated line being calculated from an estimated distance between the monitoring apparatus and the one wireless communications apparatus, based on the hop count; correcting by each monitoring apparatus, the calculated estimated line based on information indicating a node-less area in which no wireless communications apparatus of the given area is present; and determining the position of the one w
    Type: Application
    Filed: March 3, 2015
    Publication date: June 25, 2015
    Applicant: Fujitsu Limited
    Inventors: Toshiya OTOMO, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Koji Kurihara, Yuta Teranishi
  • Publication number: 20150181528
    Abstract: A sensor node executes any one among a first operation by which another sensor node is requested to execute data process and if the request is not accepted the sensor node starts executing the data processing after waiting for charging and a second operation by which the sensor node starts executing the data processing after waiting for charging, without requesting the data processing to be executed. The sensor node compares an expected value of a first time that elapses until execution is started by the sensor node or the other sensor node when the first operation is executed, and a second time that elapses until execution is started by the sensor node when the second operation is executed. Based on the comparison result, the sensor node executes among the first operation and the second operation, the operation for which the time that elapses until execution is started is shorter.
    Type: Application
    Filed: February 27, 2015
    Publication date: June 25, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Hiromasa YAMAUCHI, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Toshiya Otomo, Yuta Teranishi
  • Publication number: 20150169456
    Abstract: A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present.
    Type: Application
    Filed: February 24, 2015
    Publication date: June 18, 2015
    Inventors: Takahisa SUZUKI, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara
  • Publication number: 20150169480
    Abstract: A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.
    Type: Application
    Filed: February 24, 2015
    Publication date: June 18, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Hiromasa YAMAUCHI, Koichiro YAMASHITA, Takahisa SUZUKI, Koji KURIHARA
  • Publication number: 20150172791
    Abstract: A given communications apparatus is included among plural first communications apparatuses, among which at least execution results of data processing of the given communications apparatus is communicated by multi-hop communication whereby, the execution results are transmitted to a second communications apparatus that performs a process based on the execution results.
    Type: Application
    Filed: February 26, 2015
    Publication date: June 18, 2015
    Applicant: Fujitsu Limited
    Inventors: Hiromasa YAMAUCHI, Koichiro YAMASHITA, Takahisa SUZUKI, Koji KURIHARA, Toshiya OTOMO, Yuta TERANISHI