Abstract: After a MOS type transistor is formed on the surface of a semiconductor substrate, an interlayer insulating film covering the transistor is formed. The insulating film includes a silicon oxide film made of hydrogen silsesquioxane resin in a ceramic state. After a wiring layer is formed on the insulating film, a silicon oxide film as a surface protection film is formed on the insulating film, covering the wiring layer. In order to reduce process damages, heat treatment is performed 30 minutes at 400° C. in a nitrogen gas atmosphere. With this heat treatment, hydrogen in the silicon oxide film is released and diffuses into the channel region of the transistor to lower interfacial energy levels. Since the silicon nitride film does not transmit hydrogen, it is not necessary for the heat treatment atmosphere to contain hydrogen. A variation in threshold voltages of MOS type transistors can be easily lowered.

Abstract: A plurality of intermediate layers are formed on a base layer. Each of the intermediate layers include a conductive pad which is formed on both the insulating film of the immediately preceding layer and an interlayer insulating film which is formed on both the conductive pad of the same intermediate layer and the insulating film of the preceding intermediate layer. A plurality of through holes are formed in each of the interlayer insulating films and are filled with conductive material. The conductive pad of each intermediate layer is in electrical contact with the conductive material in the through holes of the top most intermediate layer. An insulating film is formed on both this conductive pad and the insulating film of the top most intermediate layer. A hole is formed in this insulating film which hole is substantially the same size as the conductive pad. A bonding pad is formed on the conductive pad in the through hole.

Abstract: A semiconductor device having a semiconductor substrate and a bonding pad portion formed on the semiconductor substrate, the bonding pad portion having: an insulating film formed on the semiconductor substrate and a first-level conductive pad layer of a large island shape formed on the insulating film; first-level to (n−1)-level (n is an integer of 3 or larger) interlayer insulating films formed on and over the insulating film; second-level to n-level conductive pad layers formed on the interlayer insulating films in areas generally corresponding to an area where the first conductive pad layer was formed; a plurality of small diameter first through holes from the first-level to (n−1) level formed through the first-level to (n−1) level interlayer insulating films in areas generally corresponding to an area where the first conductive pad layer; a plurality of first contact plugs filled in the small diameter first through holes from the first-level to (n−1)-level, the first contact plugs

Abstract: A hydrogen silsesquloxane resin film is formed flat by spin-coating or another such method on the surface of a semiconductor substrate or another such treatment wafer 38, after which the above-mentioned resin film is subjected to a heat treatment in an inert gas atmosphere to form a silicon oxide film of preceramic phase. In a hot plate type of heating apparatus, the wafer 38 is placed on a conveyor belt 34 and moved above a heat-generating block 30, which heats the wafer in the open air and converts the preceramic-phase silicon oxide film into a ceramic-phase silicon oxide film. The silane generated during heating does not adhere to the wafer surface as SiO2 particles, so no microscopic protrusions are produced. N2 or another such inert gas may be blown at the wafer 38 during heating.

Abstract: In a wiring forming method according to the present invention, an insulating layer is formed on a semiconductor substrate, and contact holes are formed in the insulating layer. A titanium layer is deposited on the insulating layer so as to be along inner surfaces of the contact holes. A first titanium nitride layer is formed on the titanium layer including the titanium layer formed in the contact holes. The deposition of the first titanium nitride layer is carried out under atmosphere which substantially includes no oxygen. A titanium oxynitride layer is deposited on the first titanium nitride layer. A second titanium nitride layer is deposited on the titanium oxynitride layer. Buried plugs are formed on the second titanium nitride layer formed in the contact holes. A wiring connected to the buried plugs are formed on the insulating layer. A barrier metal layer and the buried plugs are thus formed in the contact holes. According to such the structure, a stable electric contact can be obtained.

Abstract: In a wiring forming method according to the present invention, an insulating layer is formed on a semiconductor substrate, and contact holes are formed in the insulating layer. A titanium layer is deposited on the insulating layer so as to be along inner surfaces of the contact holes. A first titanium nitride layer is formed on the titanium layer including the titanium layer formed in the contact holes. The deposition of the first titanium nitride layer is carried out under atmosphere which substantially includes no oxygen. A titanium oxynitride layer is deposited on the first titanium nitride layer. A second titanium nitride layer is deposited on the titanium oxynitride layer. Buried plugs are formed on the second titanium nitride layer formed in the contact holes. A wiring connected to the buried plugs are formed on the insulating layer. A barrier metal layer and the buried plugs are thus formed in the contact holes. According to such the structure, a stable electric contact can be obtained.

Abstract: A method of fabricating a semiconductor device having a multi-layered wiring and including dummy wiring not contributing to connection of circuit elements, comprising the steps of: a) preliminarily preparing relationship between width of an isolated lower level wiring and thickness of an interlayer insulating layer with a planarized function formed on the isolated lower level wiring; b) preparing experimental results by forming dense wiring patterns in a first region on a semiconductor substrate, forming an interlayer insulating layer with a planarized function thereon, and measuring thickness of the interlayer insulating layer; c) determining a width of a dummy wiring to be disposed below an isolated upper level wiring, based on the relationship and the measuremental result; d) forming dense lower level wirings in a first region on another semiconductor substrate and a single lower level wiring having the desired width as a dummy wiring only at a location where an upper level wiring is to be formed in a seco

Abstract: An interlayer insulating film made of insulating material is deposited on a substrate having a conductive region at least partially on the surface area thereof. A connection hole is formed through the interlayer insulating film, to expose the conductive region. The connection hole is filled with a plug made of conductive material. An underlying layer made of Ti is deposited over the whole surface of the substrate including the surface of the plug. A wiring layer made of Al alloy is deposited on the underlying layer, without exposing the substrate to the external atmosphere after the deposition of the Ti layer. The wiring layer is reflowed by heating the substrate. A method is provided which is capable of connecting an upper wiring layer to a lower conductive region without lowering resistance to electromigration and lowering step coverage.

Abstract: A method of fabricating a semiconductor device having a multi-layered wiring and including dummy wiring not contributing to connection of circuit elements, comprising the steps of: a) preliminarily preparing relationship between width of an isolated lower level wiring and thickness of an interlayer insulating layer with a planarized function formed on the isolated lower level wiring; b) preparing experimental results by forming dense wiring patterns in a first region on a semiconductor substrate, forming an interlayer insulating layer with a planarized function thereon, and measuring thickness of the interlayer insulating layer; c) determining a width of a dummy wiring to be disposed below an isolated upper level wiring, based on the relationship and the measuremental result; d) forming dense lower level wirings in a first region on another semiconductor substrate and a single lower level wiring having the desired width as a dummy wiring only at a location where an upper level wiring is to be formed in a seco

Abstract: A wiring layer 36A is formed by sputtering, reflowing and patterning of an Al alloy layer on insulating layers 32 and 34 covering the surface of a semiconductor substrate 30. A silicon oxide layer 38 is formed by coating a hydrogen silsesquioxane resin film flatly over the layer 36A and by successive heat treatment. Then a silicon oxide layer 40 is formed on the layer 38 by plasma-enhanced chemical vapor deposition. After formation of the desired connecting hole in an interlayer insulating layer made of a lamination of the layers 38 and 40, a wiring layer 46 connected with the layer 36A via the connecting hole is formed by sputtering, reflowing and patterning of an Al alloy layer. Results of the measurements of the resistance of the via chains having 20000 vias indicated that resistace rise has not been observed. A multi-layered wiring which is highly resistant to stress migration is provided.

Abstract: After wiring patterns are formed on an insulating film covering the surface of a substrate, an insulating film such as plasma CVD SiO.sub.2 is formed covering the wiring patterns. A hydrogen silsesquioxane resin film with a flat surface is formed by spin coating or the like on the insulating film. Thereafter, the resin film is changed into a pre-ceramic silicon oxide film by performing heat treatment in an inert gas atmosphere. On this pre-ceramic silicon oxide film, an insulating film such as plasma enhanced CVD SiO.sub.2 film is formed and another wiring layer is formed on the insulating film. This method of forming a multi-layer wiring structure allows an interlayer insulating film to be planarized, and improves a yield of wiring formation.

Abstract: A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.

Abstract: On a first insulating film covering a substrate, wiring layer patterns are formed. Thereafter, a second insulating film of plasma CVD--SiO.sub.2 or the like is formed thereon. A hydrogen silsesquioxane resin film having a flat surface is spin-coated on the second insulating film. Thereafter, the resin film is subjected to a first heat treatment in an inert gas atmosphere to convert the resin film into a silicon oxide film of a preceramic phase. This preceramic silicon oxide film is subjected to a second heat treatment in an oxidizing atmosphere to convert this preceramic silicon oxide film into a silicon oxide film of a ceramic phase. In this case, a fine size projection is generated on the surface of the ceramic silicon oxide film. On the ceramic silicon oxide film, a third insulating film of plasma CVD--PSG or the like is formed which does not reflect the fine size projection. Thereafter, a fourth insulating film of plasma CVD--SiO.sub.2 is formed, followed by formation of a second wiring layer.

Abstract: After a MOS transistor having a gate electrode layer is formed on the surface of a semiconductor substrate, a first interlayer insulating film and a moisture blocking film are sequentially formed. After necessary contact holes are formed in the films, a first wiring layer is deposited and patterned together with the underlying blocking film, to form wiring layers for the connection to the transistor regions and a moisture blocking pattern covering the gate electrode layer. The first wiring layer includes a lowest Ti layer, Al alloy layer, and other layers. After a second interlayer insulating film is formed covering the first wiring layers, a second wiring layer is formed on the second interlayer insulating film. The second interlayer insulating film contains a spin-on-glass film which contains moisture.

Abstract: A MOS type transistor with a gate is formed on the surface of a semiconductor substrate, and thereafter an interlayer insulating film and a first level wiring layer on the insulating film are formed. The wiring layer is patterned to cover the gate electrode. A second level interlayer insulating film is formed covering the wiring layer 16, and a second level wiring layer is formed on the second level interlayer insulating film. The second level interlayer insulating film is a laminate of a silicon oxide film formed by plasma CVD using tetraethoxysilane, a spin-on-glass (SOG) film, and another similar silicon oxide film, sequentially formed in this order. An auxiliary electrode layer (blocking layer) of the first level wiring layer covering the gate electrode prevents moisture contents from being diffused from the second level interlayer insulating film toward the gate electrode.

Abstract: A moisture impervious film 24 such as silicon nitride is formed under an interlayer insulating film, covering the active region of an IC chip. The interlayer insulating film is formed, for example, by lamination of a silicon oxide film, a spin-on-glass (SOG) film, and another silicon oxide film. Moisture (H.sub.2 O) is intercepted by the moisture impervious film and does not reach the active region. It is possible to avoid the conductivity type inversion at the surface of a p-type well region in the active region and to suppress the corrosion of wiring layers, improving the reliability of the IC chip. The moisture impervious film is not limited to be formed at the layer under the silicon oxide film, but it is sufficient only if the film is formed at the layer under the SOG film.

Abstract: A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.

Abstract: On a first insulating film covering a substrate, wiring layer patterns are formed and thereafter, a second insulating film of plasma CVD--SiO.sub.2 or the like is formed thereon. A hydrogen silsesquioxane resin film having a flat surface is spin-coated on the second insulating film. Thereafter, the resin film is subjected to a first heat treatment in an inert gas atmosphere to convert the resin film into a silicon oxide film of a preceramic phase. On this silicon oxide film, a third insulating film of plasma CVD--SiO.sub.2 or the like is formed. Thereafter, a second heat treatment is performed to convert the silicon oxide film of preceramic phase into a silicon oxide film of a ceramic phase, while preventing fine size projections from being formed on the surface of the silicon oxide film. Thereafter, a second wiring layer is formed on the third insulating film. It is possible to planarize an interlevel insulating film and improve a process yield.

Abstract: A moisture impervious film 24 such as silicon nitride is formed under an interlayer insulating film, covering the active region of an IC chip. The interlayer insulating film is formed, for example, by lamination of a silicon oxide film, a spin-on-glass (SOG) film, and another silicon oxide film. Moisture (H.sub.2 O) is intercepted by the moisture impervious film and does not reach the active region. It is possible to avoid the conductivity type inversion at the surface of a p-type well region in the active region and to suppress the corrosion of wiring layers, improving the reliability of the IC chip. The moisture impervious film is not limited to be formed at the layer under the silicon oxide film, but it is sufficient only if the film is formed at the layer under the SOG film.

Abstract: A method of manufacturing a semiconductor device having the steps of: forming an insulating layer on a substrate having a semiconductor surface; forming a contact hole in and through the insulating layer; forming a conductive film on the inner surface of the contact hole and on the surface of the insulating film; forming a vapor deposited titanium film on the inner wall of a vacuum chamber; placing the substrate formed with the conductive film in the vacuum chamber; and heating the substrate and reflowing the conductive film. A good wiring layer can be formed by suppressing generation of a void during a reflow process.