Abstract: To form p-type semiconductor regions in a gallium nitride (GaN)-based semiconductor by ion implantation. A method for manufacturing a semiconductor device comprises forming first grooves, depositing, and ion-implanting. At the step of forming the first grooves, the first grooves are formed in a stacked body including a gallium nitride (GaN)-based first semiconductor layer containing an n-type impurity and a gallium nitride (GaN)-based second semiconductor layer stacked on the first semiconductor layer and containing a p-type impurity. The first grooves each have a bottom portion located in the first semiconductor layer. At the depositing step, the p-type impurity is deposited on side portions and the bottom portions of the first grooves. At the ion-implanting step, the p-type impurity is ion-implanted into the first semiconductor layer through the first grooves.

Abstract: To suppress breakage of a diode. A semiconductor device comprises a stacked body and a first electrode. The stacked body includes a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, and a fourth nitride semiconductor layer that are stacked in sequence. The first electrode is in contact with a surface of the first nitride semiconductor layer that is opposite to a surface in contact with the second nitride semiconductor layer. The semiconductor device includes a transistor forming region and a diode forming region adjacent to the transistor forming region. The transistor forming region includes a first groove, a second electrode, and a third electrode. The first groove has a bottom portion located in the second nitride semiconductor layer. The second electrode is formed on a surface of the first groove.

Abstract: A technique that recovers from degradation in crystalline nature in an ion-implanted region is provided. A method of manufacturing a semiconductor device, includes: an ion implantation step of ion-implanting p-type impurities by a cumulative dose D into an n-type semiconductor layer containing n-type impurities; and a thermal annealing step of annealing an ion-implanted region of the n-type semiconductor layer where the p-type impurities are ion-implanted, in an atmosphere containing nitrogen, at a temperature T for a time t, wherein the cumulative dose D, the temperature T, and the time t satisfy a predetermined relationship.

Abstract: A method for manufacturing a semiconductor device comprises forming first groove, depositing, and ion-implanting. At the step of forming the first groove, the first groove is formed in a stacked body comprising a gallium nitride (GaN)-based first semiconductor layer containing an n-type impurity and a gallium nitride (GaN)-based second semiconductor layer stacked on the first semiconductor layer and containing a p-type impurity. The first groove has a bottom portion located in the second semiconductor layer. At the depositing step, a p-type impurity is deposited on side portion and the bottom portion of the first groove. At the ion-implanting step, a p-type impurity is ion-implanted into the first semiconductor layer through the first groove.

Abstract: To suppress breakage of a diode. A semiconductor device comprises a stacked body and a first electrode. The stacked body includes a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, and a fourth nitride semiconductor layer that are stacked in sequence. The first electrode is in contact with a surface of the first nitride semiconductor layer that is opposite to a surface in contact with the second nitride semiconductor layer. The semiconductor device includes a transistor forming region and a diode forming region adjacent to the transistor forming region. The transistor forming region includes a first groove, a second electrode, and a third electrode. The first groove has a bottom portion located in the second nitride semiconductor layer. The second electrode is formed on a surface of the first groove.

Abstract: To form p-type semiconductor regions in a gallium nitride (GaN)-based semiconductor by ion implantation. A method for manufacturing a semiconductor device comprises forming first grooves, depositing, and ion-implanting. At the step of forming the first grooves, the first grooves are formed in a stacked body including a gallium nitride (GaN)-based first semiconductor layer containing an n-type impurity and a gallium nitride (GaN)-based second semiconductor layer stacked on the first semiconductor layer and containing a p-type impurity. The first grooves each have a bottom portion located in the first semiconductor layer. At the depositing step, the p-type impurity is deposited on side portions and the bottom portions of the first grooves. At the ion-implanting step, the p-type impurity is ion-implanted into the first semiconductor layer through the first grooves.

Abstract: There is provided a method of manufacturing a nitride semiconductor device. The method of manufacturing the nitride semiconductor device comprises: a first film forming process that forms a first film on a nitride semiconductor layer; an ion implantation process that implants a P-type impurity into the nitride semiconductor layer through the first film by ion implantation; a second film forming process that forms a second film on the first film, after the ion implantation process; and a heat treatment process that processes the nitride semiconductor layer by heat treatment after the second film forming process. This suppresses the surface of the nitride semiconductor layer from being roughened.

Abstract: There is provided a method of manufacturing a semiconductor device.

Abstract: A method for manufacturing a semiconductor device comprises forming first groove, depositing, and ion-implanting. At the step of forming the first groove, the first groove is formed in a stacked body comprising a gallium nitride (GaN)-based first semiconductor layer containing an n-type impurity and a gallium nitride (GaN)-based second semiconductor layer stacked on the first semiconductor layer and containing a p-type impurity. The first groove has a bottom portion located in the second semiconductor layer. At the depositing step, a p-type impurity is deposited on side portion and the bottom portion of the first groove. At the ion-implanting step, a p-type impurity is ion-implanted into the first semiconductor layer through the first groove.

Abstract: A technique that recovers from degradation in crystalline nature in an ion-implanted region is provided. A method of manufacturing a semiconductor device, includes: an ion implantation step of ion-implanting p-type impurities by a cumulative dose D into an n-type semiconductor layer containing n-type impurities; and a thermal annealing step of annealing an ion-implanted region of the n-type semiconductor layer where the p-type impurities are ion-implanted, in an atmosphere containing nitrogen, at a temperature T for a time t, wherein the cumulative dose D, the temperature T, and the time t satisfy a predetermined relationship.

Abstract: There is provided a manufacturing method of a semiconductor device. The manufacturing method of the semiconductor device comprises: forming at least part of a cap layer that is mainly composed of a nitride, on a semiconductor layer that is mainly composed of a group III nitride semiconductor; implanting a p-type impurity into the semiconductor layer with at least part of the cap layer formed thereon, by ion implantation; forming a block layer having a larger coefficient of thermal expansion than a coefficient of thermal expansion of the cap layer, as a surface layer on the cap layer; and heating the semiconductor layer with the block layer as the surface layer, to activate the p-type impurity.

Abstract: There is provided an MPS diode comprising a first semiconductor layer that is an N type; P-type semiconductor regions and N-type semiconductor regions that are arranged alternately on one surface of the first semiconductor layer; and a Schottky electrode that is in Schottky junction with the N-type semiconductor regions and is arranged to be adjacent to and in contact with at least part of the P-type semiconductor regions. A donor concentration in an area of the N-type semiconductor region that is adjacent to and in contact with the first semiconductor layer is lower than the donor concentration in an area of the first semiconductor layer that is adjacent to and in contact with the N-type semiconductor region and is lower than the donor concentration in an area of the N-type semiconductor region that is adjacent to and in contact with the Schottky electrode. This configuration improves a breakdown voltage under applying a reverse bias voltage and reduces a rising voltage under applying a forward bias voltage.

Abstract: There is provided a manufacturing method of a semiconductor device. The manufacturing method of the semiconductor device comprises: forming at least part of a cap layer that is mainly composed of a nitride, on a semiconductor layer that is mainly composed of a group III nitride semiconductor; implanting a p-type impurity into the semiconductor layer with at least part of the cap layer formed thereon, by ion implantation; forming a block layer having a larger coefficient of thermal expansion than a coefficient of thermal expansion of the cap layer, as a surface layer on the cap layer; and heating the semiconductor layer with the block layer as the surface layer, to activate the p-type impurity.

Abstract: The method for manufacturing comprises an ion implantation process of implanting a p-type impurity into a semiconductor layer mainly made of a group III nitride by ion implantation; a first heating process of heating the semiconductor layer at a first temperature in a first atmospheric gas including ammonia (NH3) after the ion implantation process; and a second heating process of heating the semiconductor layer, after the first heating process, at a second temperature that is lower than the first temperature in a second atmospheric gas including oxygen (O2).

Abstract: A technique of reducing the manufacturing cost of a semiconductor device is provided, There is provided a method of manufacturing a semiconductor device comprising an ion implantation process of implanting at least one of magnesium and beryllium by ion implantation into a first semiconductor layer that is mainly formed from a group III nitride; and a heating process of heating the first semiconductor layer in an atmosphere that includes an anneal gas of at least one of magnesium and beryllium, after the ion implantation process.

Abstract: A technique of reducing the manufacturing cost of a semiconductor device is provided, There is provided a method of manufacturing a semiconductor device comprising an ion implantation process of implanting at least one of magnesium and beryllium by ion implantation into a first semiconductor layer that is mainly formed from a group III nitride; and a heating process of heating the first semiconductor layer in an atmosphere that includes an anneal gas of at least one of magnesium and beryllium, after the ion implantation process,

Abstract: There is provided an MPS diode comprising a first semiconductor layer that is an N type; P-type semiconductor regions and N-type semiconductor regions that are arranged alternately on one surface of the first semiconductor layer; and a Schottky electrode that is in Schottky junction with the N-type semiconductor regions and is arranged to be adjacent to and in contact with at least part of the P-type semiconductor regions. A donor concentration in an area of the N-type semiconductor region that is adjacent to and in contact with the first semiconductor layer is lower than the donor concentration in an area of the first semiconductor layer that is adjacent to and in contact with the N-type semiconductor region and is lower than the donor concentration in an area of the N-type semiconductor region that is adjacent to and in contact with the Schottky electrode. This configuration improves a breakdown voltage under applying a reverse bias voltage and reduces a rising voltage under applying a forward bias voltage.

Abstract: An object is to provide a technique that suppresses decrease in the breakdown voltage of a protective element. There is provided a semiconductor device that comprises a vertical MOS transistor and a protective element. A first nitride semiconductor layer has a convex that is protruded toward a second nitride semiconductor layer. The convex has a top face placed at a position to overlap with at least part of an ohmic electrode of a second conductive type when viewed from a stacking direction of a stacked body. The thickness of the second nitride semiconductor layer in a portion which a bottom face of a trench is in contact with is greater than the thickness of the second nitride semiconductor layer in a portion which the top face of the convex is in contact with.

Abstract: There is provided a method of manufacturing a nitride semiconductor device. The method of manufacturing the nitride semiconductor device comprises: a first film forming process that forms a first film on a nitride semiconductor layer; an ion implantation process that implants a P-type impurity into the nitride semiconductor layer through the first film by ion implantation; a second film forming process that forms a second film on the first film, after the ion implantation process; and a heat treatment process that processes the nitride semiconductor layer by heat treatment after the second film forming process. This suppresses the surface of the nitride semiconductor layer from being roughened.

Abstract: There is provided a method of manufacturing a semiconductor device.