Patents by Inventor Takaki Niwa
Takaki Niwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160284843Abstract: An object is to provide a technique that suppresses decrease in the breakdown voltage of a protective element. There is provided a semiconductor device that comprises a vertical MOS transistor and a protective element. A first nitride semiconductor layer has a convex that is protruded toward a second nitride semiconductor layer. The convex has a top face placed at a position to overlap with at least part of an ohmic electrode of a second conductive type when viewed from a stacking direction of a stacked body. The thickness of the second nitride semiconductor layer in a portion which a bottom face of a trench is in contact with is greater than the thickness of the second nitride semiconductor layer in a portion which the top face of the convex is in contact with.Type: ApplicationFiled: March 9, 2016Publication date: September 29, 2016Inventors: Takaki NIWA, Masayoshi Kosaki, Takahiro Fujii, Tohru Oka, Yukihisa Ueno
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Publication number: 20160284563Abstract: The method for manufacturing comprises an ion implantation process of implanting a p-type impurity into a semiconductor layer mainly made of a group III nitride by ion implantation; a first heating process of heating the semiconductor layer at a first temperature in a first atmospheric gas including ammonia (NH3) after the ion implantation process; and a second heating process of heating the semiconductor layer, after the first heating process, at a second temperature that is lower than the first temperature in a second atmospheric gas including oxygen (O2).Type: ApplicationFiled: March 3, 2016Publication date: September 29, 2016Inventors: Takaki NIWA, Tohru Oka, Masayoshi Kosaki, Takahiro Fujii, Yukihisa Ueno
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Patent number: 7834461Abstract: A semiconductor apparatus includes a semiconductor device formed to a first surface of a semiconductor substrate, a blocking film provided in a first via-hole, the first via-hole formed with a concave shape to the first surface of the semiconductor substrate, a first via line connected to an electrode of the semiconductor device in contact with the blocking film, a second via line formed inside a second via-hole, electrically connected with the first via line with the blocking film interposed therebetween and being apart of a wiring formed to a second surface, the second via-hole formed with a concave shape to the second surface opposing the first surface of the semiconductor substrate so as to reach the blocking film. The blocking film includes at least one kind of group 8 element.Type: GrantFiled: September 11, 2007Date of Patent: November 16, 2010Assignee: NEC Electronics CorporationInventors: Shuji Asai, Tadachika Hidaka, Naoto Kurosawa, Hirokazu Oikawa, Takaki Niwa
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Patent number: 7821037Abstract: A heterojunction bipolar transistor includes a first conductivity type subcollector layer, a first collector layer containing a first conductivity type impurity, a third collector layer containing a higher concentration of the first conductivity type impurity than the first collector layer, a second collector layer containing a lower concentration of the first conductivity type impurity than the first collector layer, a second conductivity type base layer, a first conductivity type emitter layer containing a semiconductor with a wider bandgap than the base layer, and a first conductivity type emitter cap layer.Type: GrantFiled: November 16, 2007Date of Patent: October 26, 2010Assignee: NEC Electronics CorporationInventors: Takaki Niwa, Naoto Kurosawa
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Publication number: 20080116489Abstract: A heterojunction bipolar transistor includes a first conductivity type subcollector layer, a first collector layer containing a first conductivity type impurity, a third collector layer containing a higher concentration of the first conductivity type impurity than the first collector layer, a second collector layer containing a lower concentration of the first conductivity type impurity than the first collector layer, a second conductivity type base layer, a first conductivity type emitter layer containing a semiconductor with a wider bandgap than the base layer, and a first conductivity type emitter cap layer.Type: ApplicationFiled: November 16, 2007Publication date: May 22, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Takaki Niwa, Naoto Kurosawa
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Publication number: 20080073752Abstract: A semiconductor apparatus includes a semiconductor device formed to a first surface of a semiconductor substrate, a blocking film provided in a first via-hole, the first via-hole formed with a concave shape to the first surface of the semiconductor substrate, a first via line connected to an electrode of the semiconductor device in contact with the blocking film, a second via line formed inside a second via-hole, electrically connected with the first via line with the blocking film interposed therebetween and being apart of a wiring formed to a second surface, the second via-hole formed with a concave shape to the second surface opposing the first surface of the semiconductor substrate so as to reach the blocking film. The blocking film includes at least one kind of group 8 element.Type: ApplicationFiled: September 11, 2007Publication date: March 27, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Shuji ASAI, Tadachika HIDAKA, Naoto KUROSAWA, Hirokazu OIKAWA, Takaki NIWA
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Patent number: 7304333Abstract: A heterojunction bipolar transistor, having a structure in which a subcollector layer of a first conductive type having a higher doping concentration than a collector layer, a collector layer of the first conductive type, a base layer of the second conductive type, and an emitter layer of the first conductive type are deposited, in order, on a semi-insulating semiconductor substrate, and in which a hole barrier layer of semiconductor material with a band gap wider than that of the base layer is inserted between the base layer and the collector layer, so as to be in direct contact with the base layer.Type: GrantFiled: October 29, 2004Date of Patent: December 4, 2007Assignee: NEC Compound Semiconductor Devices, Ltd.Inventor: Takaki Niwa
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Patent number: 7038244Abstract: A semiconductor device includes a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer, which are sequentially laminated on a substrate. It also includes an emitter electrode, a base electrode, and a collector electrode, which are respectively formed on the emitter cap layer, the base layer, and the sub-collector layer. The sub-collector layer is made up of a first sub-collector layer adjacent to the substrate and a second sub-collector layer adjacent to the collector layer. In the area between adjacent device elements, the first sub-collector layer has an element insulating region created by ion implantation, and the second sub-collector layer has a recess-shaped element insulating region.Type: GrantFiled: November 23, 2004Date of Patent: May 2, 2006Assignees: NEC Compound Semiconductor Devices, Ltd., NEC CorporationInventors: Takashi Ishigaki, Takaki Niwa, Naoto Kurosawa, Hidenori Shimawaki
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Publication number: 20050110045Abstract: A semiconductor device includes a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer, which are sequentially laminated on a substrate. It also includes an emitter electrode, a base electrode, and a collector electrode, which are respectively formed on the emitter cap layer, the base layer, and the sub-collector layer. The sub-collector layer is made up of a first sub-collector layer adjacent to the substrate and a second sub-collector layer adjacent to the collector layer. In the area between adjacent device elements, the first sub-collector layer has an element insulating region created by ion implantation, and the second sub-collector layer has a recess-shaped element insulating region.Type: ApplicationFiled: November 23, 2004Publication date: May 26, 2005Applicants: NEC Compound Semiconductor Devices, Ltd., NEC CorporationInventors: Takashi Ishigaki, Takaki Niwa, Naoto Kurosawa, Hidenori Shimawaki
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Publication number: 20050104088Abstract: A heterojunction bipolar transistor, having a structure in which a subcollector layer of a first conductive type having a higher doping concentration than a collector layer, a collector layer of the first conductive type, a base layer of the second conductive type, and an emitter layer of the first conductive type are deposited, in order, on a semi-insulating semiconductor substrate, and in which a hole barrier layer of semiconductor material with a band gap wider than that of the base layer is inserted between the base layer and the collector layer, so as to be in direct contact with the base layer.Type: ApplicationFiled: October 29, 2004Publication date: May 19, 2005Applicant: NEC Compound Semiconductor Devices, Ltd.Inventor: Takaki Niwa
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Patent number: 6881988Abstract: A heterojunction bipolar transistor has a raised breakdown voltage and restrains the rising characteristic of IC-VCE characteristic from degrading. The collector region includes first, second, and third collector layers of semiconductor. The first collector layer is made of a doped or undoped semiconductor in such a way as to contact the sub-collector region. The second collector layer is made of a doped or undoped semiconductor having a narrower band gap than the first collector layer in such a way as to contact the base region. The third collector layer has a higher doping concentration than the second collector layer in such a way as to be located between or sandwiched by the first collector layer and the second collector layer.Type: GrantFiled: August 14, 2002Date of Patent: April 19, 2005Assignee: NEC Compound Semiconductor Devices, Ltd.Inventors: Takaki Niwa, Hidenori Shimawaki, Koji Azuma, Naoto Kurosawa
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Publication number: 20030136956Abstract: A heterojunction bipolar transistor has a raised breakdown voltage and restrains the rising characteristic of IC-VCE characteristic from degrading. The collector region includes first, second, and third collector layers of semiconductor. The first collector layer is made of a doped or undoped semiconductor in such a way as to contact the sub-collector region. The second collector layer is made of a doped or undoped semiconductor having a narrower band gap than the first collector layer in such a way as to contact the base region. The third collector layer has a higher doping concentration than the second collector layer in such a way as to be located between or sandwiched by the first collector layer and the second collector layer.Type: ApplicationFiled: August 14, 2002Publication date: July 24, 2003Applicant: NEC Compound Semiconductor Devices, Ltd.Inventors: Takaki Niwa, Hidenori Shimawaki, Koji Azuma, Naoto Kurosawa
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Publication number: 20020195620Abstract: A heterojunction bipolar transistor and a protective PIN diode are implemented by two multi-layered compound semiconductor structures epitaxially grown on respective regions of a semi-insulating substrate; the entire upper surface of the base layer is covered with the emitter layer, and the base electrode on the emitter layer projects through the emitter layer into the base layer; although the two multi-layered compound semiconductor structures are covered with a passivation layer, the emitter layer prevents the base layer from direct contact with the passivation layer so that leakage current hardly flows between the base and the emitter.Type: ApplicationFiled: June 5, 2002Publication date: December 26, 2002Applicant: NEC Compound Semiconductor Devices, Ltd.Inventors: Masahiro Tanomura, Hidenori Shimawaki, Takaki Niwa, Koji Azuma, Naoto Kurosawa
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Patent number: 6355947Abstract: A heterojunction bipolar transistor having reduced parasitic emitter resistance. The bipolar transistor comprises a semi-insulating substrate, a collector contact layer formed on the semi-insulating substrate, a collector layer formed on the collector contact layer, a base layer formed on the collector layer, an emitter layer formed on the base layer, a composition graded layer formed on the emitter layer, and an emitter contact layer formed on the composition graded layer. A forbidden band width of the emitter layer is wider than that of the base layer. A forbidden band width of the emitter contact layer is narrower than that of the emitter layer and impurity concentration of the emitter contact layer is higher than that of the emitter layer.Type: GrantFiled: July 21, 1999Date of Patent: March 12, 2002Assignee: NEC CorporationInventor: Takaki Niwa
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Patent number: 5959317Abstract: A hetero junction type field effect transistor can control a short channel effect, reduce the fluctuation of a threshold, and improve a yield. The hetero junction type field effect transistor comprises: a semiconductor substrate, a first electron feed layer made of a doped semiconductor having a wider band gap than the channel layer, a channel layer made of a non-doped semiconductor, a second electron feed layer comprising a laminate structure of a plurality of semiconductor layers having a wider band gap than the channel layer and having a thickness of 100 .ANG. or less, and a gate electrode, a source electrode, and a drain electrode.Type: GrantFiled: November 26, 1997Date of Patent: September 28, 1999Assignee: NEC CorporationInventor: Takaki Niwa