Patents by Inventor Takako Takehara
Takako Takehara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7086918Abstract: An organic electroluminescent device comprising an anode layer on a substrate, an organic layer on the anode layer, and a cathode layer on the organic layer. In one embodiment, the cathode layer is subjected to H2 plasma prior to deposition of a protective layer over the cathode. In another embodiment, the organic electroluminescent device is encapsulated with an inner encapsulation layer on the cathode layer, and an outer encapsulation layer on the inner encapsulation layer. The inner layer is optimized for adhesion to the cathode layer.Type: GrantFiled: December 11, 2002Date of Patent: August 8, 2006Assignee: Applied Materials, Inc.Inventors: Mark Hsiao, Takako Takehara, Quanyuan Shang, William R. Harshbarger
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Patent number: 6962732Abstract: Processes for controlling thickness uniformity of thin organosilicate films as they are deposited on a substrate, and as they finally result. During deposition of the film, which may be accomplished by CVD, PECVD, rapid thermal processing or the like, the substrate temperature is controlled to establish a temperature profile particularly suited to the extreme temperature sensitivities of the deposition rates of organosilicate films such as those deposited from TEOS as a source material.Type: GrantFiled: August 23, 2001Date of Patent: November 8, 2005Assignee: Applied Materials, Inc.Inventors: Tae Kyung Won, Takako Takehara, William R. Harshbarger
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Publication number: 20050233155Abstract: Processes for controlling thickness uniformity of thin organosilicate films as they are deposited on a substrate, and as they finally result. During deposition of the film, which may be accomplished by CVD, PECVD, rapid thermal processing or the like, the substrate temperature is controlled to establish a temperature profile particularly suited to the extreme temperature sensitivities of the deposition rates of organosilicate films such as those deposited from TEOS as a source material.Type: ApplicationFiled: June 8, 2005Publication date: October 20, 2005Inventors: Tae Won, Takako Takehara, William Harshbarger
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Patent number: 6827987Abstract: Provided herein is a method of reducing an electrostatic charge on a substrate during a plasma enhanced chemical vapor deposition process, comprising the step of depositing a conductive layer onto a top surface of a susceptor support plate disposed within a deposition chamber wherein the conductive layer dissipates the electrostatic charge on the bottom surface of the substrate during a plasma enhanced chemical vapor deposition process. Also provided are a method of depositing a thin film during a plasma enhanced chemical vapor deposition process using the methods disclosed herein and a conductive susceptor.Type: GrantFiled: July 27, 2001Date of Patent: December 7, 2004Assignee: Applied Materials, Inc.Inventors: Tae Kyung Won, Soo Young Choi, Takako Takehara, William R. Harshbarger
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Publication number: 20040241920Abstract: Method of fabricating a thin-film transistor (TFT) in which a gate metal is deposited onto a substrate in order to form the gate of the thin-film transistor. The substrate may be an insulative substrate or a color filter. In a first method, the gate metal is subjected to an H2 plasma. After subjecting the gate metal to an H2 plasma, the gate insulating film is deposited onto the gate. In a second method, first and second layers of gate insulating film are respectively deposited on the gate at a first and second deposition rates. One layer is deposited under H2 or argon dilution conditions and has improved insulating conditions while the other layer serves to lower the overall compressive stress of the dual layer gate insulator. In a third method, an n+ silicon film is formed on a substrate by maintaining a flow of silane, phosphine and hydrogen gas into a processing chamber at substrate temperatures of about 300° C. or less.Type: ApplicationFiled: June 2, 2003Publication date: December 2, 2004Applicants: Applied Materials, Inc., LG Philips Displays USA, Inc.Inventors: Mark Hsiao, Dong-Kil Yim, Takako Takehara, Quanyuan Shang, William R. Harshbarger, Woong-Kwon Kim, Duk-Chul Yun, Youn-Gyung Chang
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Publication number: 20040113542Abstract: An organic electroluminescent device comprising an anode layer on a substrate, an organic layer on the anode layer, and a cathode layer on the organic layer. In one embodiment, the cathode layer is subjected to H2 plasma prior to deposition of a protective layer over the cathode. In another embodiment, the organic electroluminescent device is encapsulated with an inner encapsulation layer on the cathode layer, and an outer encapsulation layer on the inner encapsulation layer. The inner layer is optimized for adhesion to the cathode layer.Type: ApplicationFiled: December 11, 2002Publication date: June 17, 2004Applicant: Applied Materials, Inc.Inventors: Mark Hsiao, Takako Takehara, Quanyuan Shang, William R. Harshbarger
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Publication number: 20030218424Abstract: A plasma display panel including a low k dielectric layer. In one embodiment, the dielectric layer is comprises a fluorine-doped silicon oxide layer such as an SiOF layer. In another embodiment, the dielectric layer comprises a Black Diamond™ layer. In certain embodiments, a capping layer such as SiN or SiON is deposited over the dielectric layer.Type: ApplicationFiled: June 11, 2003Publication date: November 27, 2003Applicant: Applied Materials, Inc.Inventors: Kam S. Law, Quanyuan Shang, Takako Takehara, Taekyung Won, William R. Harshbarger, Dan Maydan
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Patent number: 6610354Abstract: A plasma display panel including a low k dielectric layer. In one embodiment, the dielectric layer is comprises a fluorine-doped silicon oxide layer such as an SiOF layer. In another embodiment, the dielectric layer comprises a Black Diamond™ layer. In certain embodiments, a capping layer such as SiN or SiON is deposited over the dielectric layer.Type: GrantFiled: June 18, 2001Date of Patent: August 26, 2003Assignee: Applied Materials, Inc.Inventors: Kam S. Law, Quanyuan Shang, Takako Takehara, Taekyung Won, William R. Harshbarger, Dan Maydan
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Patent number: 6610374Abstract: A thin film layer can be formed on a glass substrate by preheating the substrate, depositing an amorphous silicon precursor layer on the substrate at a first temperature, and annealing the substrate in a thermal processing chamber at a second temperature sufficiently higher than the first temperature to substantially reduce the hydrogen concentration in the precursor layer. The preheating and annealing steps can occur in the same thermal processing chamber. Then the precursor layer is converted to a polycrystaline silicon layer by laser annealing.Type: GrantFiled: September 10, 2001Date of Patent: August 26, 2003Assignee: Applied Materials, Inc.Inventors: Chuang-Chuang Tsai, Takako Takehara, Regina Qiu, Yvonne LeGrice, William Reid Harshbarger, Robert McCormick Robertson
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Publication number: 20030044621Abstract: Processes for controlling thickness uniformity of thin organosilicate films as they are deposited on a substrate, and as they finally result. During deposition of the film, which may be accomplished by CVD, PECVD, rapid thermal processing or the like, the substrate temperature is controlled to establish a temperature profile particularly suited to the extreme temperature sensitivities of the deposition rates of organosilicate films such as those deposited from TEOS as a source material.Type: ApplicationFiled: August 23, 2001Publication date: March 6, 2003Applicant: Applied Materials, Inc.Inventors: Tae Kyung Won, Takako Takehara, William R. Harshbarger
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Publication number: 20030031792Abstract: Provided herein is a method of reducing an electrostatic charge on a substrate during a plasma enhanced chemical vapor deposition process, comprising the step of depositing a conductive layer onto a top surface of a susceptor support plate disposed within a deposition chamber wherein the conductive layer dissipates the electrostatic charge on the bottom surface of the substrate during a plasma enhanced chemical vapor deposition process. Also provided are a method of depositing a thin film during a plasma enhanced chemical vapor deposition process using the methods disclosed herein and a conductive susceptor.Type: ApplicationFiled: July 27, 2001Publication date: February 13, 2003Applicant: Applied Materials, Inc.Inventors: Tae Kyung Won, Soo Young Choi, Takako Takehara, William R. Harshbarger
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Publication number: 20020192475Abstract: A method for the deposition of a silicon dioxide film onto a substrate using plasma enhanced chemical vapor deposition and TEOS is disclosed. The method includes controlling the deposition rate of silicon dioxide on a substrate by pulsing the radio frequency power supply used to generate a TEOS oxide plasma. The obtained silicon dioxide film is good in electrical and mechanical film properties for the application of forming thin film transistors.Type: ApplicationFiled: July 19, 2002Publication date: December 19, 2002Inventors: Haruhiro H. Goto, Takako Takehara, Carl A. Sorensen, William R. Harshbarger, Kam S. Law
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Publication number: 20020190651Abstract: A plasma display panel including a low k dielectric layer. In one embodiment, the dielectric layer is comprises a fluorine-doped silicon oxide layer such as an SiOF layer. In another embodiment, the dielectric layer comprises a Black Diamond™ layer. In certain embodiments, a capping layer such as SiN or SiON is deposited over the dielectric layer.Type: ApplicationFiled: June 18, 2001Publication date: December 19, 2002Applicant: Applied Materials, Inc.Inventors: Kam S. Law, Quanyuan Shang, Takako Takehara, Taekyung Won, William R. Harshbarger, Dan Maydan
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Patent number: 6451390Abstract: A method for the deposition of a silicon dioxide film onto a substrate using plasma enhanced chemical vapor deposition and TEOS is disclosed. The method includes controlling the deposition rate of silicon dioxide on a substrate by pulsing the radio frequency power supply used to generate a TEOS oxide plasma. The obtained silicon dioxide film is good in electrical and mechanical film properties for the application of forming thin film transistors.Type: GrantFiled: April 6, 2000Date of Patent: September 17, 2002Assignee: Applied Materials, Inc.Inventors: Haruhiro H. Goto, Takako Takehara, Carl A. Sorensen, William R. Harshbarger, Kam S. Law
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Publication number: 20020115269Abstract: Deposition methods for preparing amorphous silicon based films with controlled resistivity and low stress are described. Such films can be used as the interlayer in FED manufacturing. They can also be used in other electronic devices which require films with controlled resistivity in the range between those of an insulator and of a conductor. The deposition methods described in the present invention employ the method of chemical vapor deposition or plasma-enhanced chemical vapor deposition; other film deposition techniques, such as physical vapor deposition, also may be used. In one embodiment, an amorphous silicon-based film is formed by introducing into a deposition chamber a silicon-based volatile, a conductivity-increasing volatile including one or more components for increasing the conductivity of the amorphous silicon-based film, and a conductivity-decreasing volatile including one or more components for decreasing the conductivity of the amorphous silicon-based film.Type: ApplicationFiled: November 2, 2001Publication date: August 22, 2002Applicant: Applied Materials, Inc.Inventors: William R. Harshbarger, Takako Takehara, Jeff C. Olsen, Regina Qiu, Yvonne LeGrice, Guofu J. Feng, Robert M. Robertson, Kam Law
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Patent number: 6352910Abstract: Deposition methods for preparing amorphous silicon based films with controlled resistivity and low stress are described. Such films can be used as the interlayer in FED manufacturing. They can also be used in other electronic devices which require films with controlled resistivity in the range between those of an insulator and of a conductor. The deposition methods described in the present invention employ the method of chemical vapor deposition or plasma-enhanced chemical vapor deposition; other film deposition techniques, such as physical vapor deposition, also may be used. In one embodiment, an amorphous silicon-based film is formed by introducing into a deposition chamber a silicon-based volatile, a conductivity-increasing volatile including one or more components for increasing the conductivity of the amorphous silicon-based film, and a conductivity-decreasing volatile including one or more components for decreasing the conductivity of the amorphous silicon-based film.Type: GrantFiled: February 12, 1999Date of Patent: March 5, 2002Assignee: Applied Komatsu Technology, Inc.Inventors: William R. Harshbarger, Takako Takehara, Jeff C. Olsen, Regina Qiu, Yvonne LeGrice, Guofu J. Feng, Robert M. Robertson, Kam Law
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Publication number: 20020018862Abstract: A thin film layer can be formed on a glass substrate by preheating the substrate, depositing an amorphous silicon precursor layer on the substrate at a first temperature, and annealing the substrate in a thermal processing chamber at a second temperature sufficiently higher than the first temperature to substantially reduce the hydrogen concentration in the precursor layer. The preheating and annealing steps can occur in the same thermal processing chamber. Then the precursor layer is converted to a polycrystaline silicon layer by laser annealing.Type: ApplicationFiled: September 10, 2001Publication date: February 14, 2002Applicant: Applied Kamatsu Technology, Inc.Inventors: Chuang-Chuang Tsai, Takako Takehara, Regina Qiu, Yvonne LeGrice, William Reid Harshbarger, Robert McCormick Robertson
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Patent number: 6294219Abstract: A thin film layer can be formed on a glass substrate by preheating the substrate, depositing an amorphous silicon precursor layer on the substrate at a first temperature, and annealing the substrate in a thermal processing chamber at a second temperature sufficiently higher than the first temperature to substantially reduce the hydrogen concentration in the precursor layer. The preheating and annealing steps can occur in the same thermal processing chamber. Then the precursor layer is converted to a polycrystaline silicon layer by laser annealing.Type: GrantFiled: March 3, 1998Date of Patent: September 25, 2001Assignee: Applied Komatsu Technology, Inc.Inventors: Chuang-Chuang Tsai, Takako Takehara, Regina Qiu, Yvonne LeGrice, William Reid Harshbarger, Robert McCormick Robertson
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Patent number: 6172322Abstract: A system and method for annealing a film on a substrate in a processing chamber, including a microwave generator disposed to provide microwaves to an area within the interior of the chamber. The microwaves have a frequency such that the film is substantially absorptive at the frequency but the substrate is not substantially absorptive at the frequency. A waveguide distributes the microwaves over the surface of the film to provide a substantially uniform dosage of microwaves over the surface of the film. The method includes depositing a film on a substrate in the processing chamber. During at least a portion of the time of the depositing step, microwaves are generated having a frequency such that the film has an absorption peak at the frequency but the substrate lacks a substantial absorption peak at the frequency. The microwaves are directed towards the film.Type: GrantFiled: November 7, 1997Date of Patent: January 9, 2001Assignee: Applied Technology, Inc.Inventors: Quanyuan Shang, Robert McCormick Robertson, Kam S. Law, Takako Takehara, Taekyung Won, Sheng Sun
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Patent number: 5567476Abstract: A multi-step CVD method for thin film transistor is disclosed. The method can be carried out by depositing a high quality g-SiN.sub.x at a low deposition rate on top of an average quality gate nitride deposited at a high deposition rate and then depositing an amorphous silicon layer. It also applies in a process where high quality amorphous silicon is first deposited at a low deposition rate on a gate nitride layer to form an interface, and then average quality amorphous silicon is deposited at a high deposition rate to complete the silicon layer. The unique process can be applied whenever an interface exists with an active semiconductor layer of amorphous silicon. The process is applicable to either the back channel etched TFT device or the etch stopped TFT device.Type: GrantFiled: April 25, 1995Date of Patent: October 22, 1996Assignee: Applied Komatsu Technology, Inc.Inventors: Kam S. Law, Robert Robertson, Michael Kollrack, Angela T. Lee, Takako Takehara, Guofu J. Feng, Dan Maydan