Patents by Inventor Takamasa Itou
Takamasa Itou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230235925Abstract: A refrigerant circuit includes a first compressor connected to a first suction pipe and a first discharge pipe and configured to compress a refrigerant, a second compressor connected to a second suction pipe and a second discharge pipe and configured to compress the refrigerant discharged from the first compressor, a radiator, and a high-pressure passage connecting the second discharge pipe and the radiator. A first oil drain passage guides an oil in the second compressor to one of the first suction pipe and an intermediate port of the first compressor, without via the high-pressure passage.Type: ApplicationFiled: March 29, 2023Publication date: July 27, 2023Applicant: DAIKIN INDUSTRIES, LTD.Inventors: Azuma KONDOU, Takamasa ITOU, Chiharu TOMITA
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Publication number: 20220057130Abstract: A method for controlling an operation of an ice-making machine configured to make ice by cooling a medium to be cooled, through heat exchange with a refrigerant. The method includes increasing an evaporation temperature of the refrigerant to be supplied to the ice-making machine when a drive current for an ice scraper of the ice-making machine is more than a first current value.Type: ApplicationFiled: August 28, 2019Publication date: February 24, 2022Applicant: DAIKIN INDUSTRIES, LTD.Inventors: Kouichi KITA, Akihiro KAJIMOTO, Kazuhiko NISHIHARA, Takamasa ITOU, Yuuji YAMANAKA, Takeo UENO
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Patent number: 10378406Abstract: An exhaust emission control apparatus is provided with a supply device, a catalyst, and a gas pressure reduction part. The supply device supplies a reducing agent to an exhaust passage. The catalyst purifies an exhaust gas by the use of the reducing agent. The gas pressure reduction part can make a gas pressure near the supply port lower than the gas pressure on the inside of a supply device body. A NOx catalyst adsorbs nitrogen oxide contained in the exhaust. NOx adsorbed by the NOx catalyst is desorbed from the NOx catalyst when the exhaust gas is purified. An ECU estimates an adsorption amount of NOx. Then, the ECU estimates a desorption amount of NOx desorbed from the NOx catalyst on the basis of the estimated adsorption amount of NOx.Type: GrantFiled: May 10, 2016Date of Patent: August 13, 2019Assignee: DENSO CORPORATIONInventors: Kengo Furukawa, Yusuke Hongo, Jun Osaka, Yoshiho Uchiyama, Takamasa Itou, Wakichi Kondoh, Masaki Takeyama, Kohei Motoo
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Patent number: 10018139Abstract: A fuel injection device is used in an internal combustion engine having a combustion chamber partitioned by a cylinder head, a cylinder, and a piston crown surface so that at least one of the amount of NOx, Pmax, and a thermal efficiency ? is maintained at a predetermined value. The fuel injection device includes a fuel injection change unit. The fuel injection change unit virtually divides the combustion chamber into N number of combustion zones where N is a natural number of 2 or more, and can change a fuel injection method according to the respective combustion zones. The fuel injection change unit divides the combustion chamber into the N number of combustion zones, thereby being capable of eliminating a difference of heat in the respective combustion zones, and precisely controlling an in-cylinder pressure P in the combustion chamber. As a result, the amount of NOx and the thermal efficiency can be optimized.Type: GrantFiled: June 7, 2016Date of Patent: July 10, 2018Assignee: DENSO CORPORATIONInventors: Takamasa Itou, Wakichi Kondoh, Shinichiro Kawakita
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Patent number: 9583441Abstract: A conductor provided in an interconnection layer is allowed to have a low resistance. An insulator film is provided over a substrate, and is comprised of SiO(1-x)Nx (where x>0.5 in an XRD analysis result). An interconnection is provided over the insulator film, and includes a first layer and a second layer. The first layer includes at least one of TiN, TaN, WN, and RuN. The second layer is provided over the first layer, and is formed of a material having a resistance lower than the first layer, for example, W.Type: GrantFiled: July 24, 2015Date of Patent: February 28, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Ogura, Tatsuya Usami, Satoshi Kodama, Shuuichirou Ueno, Satoshi Itou, Takamasa Itou
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Publication number: 20160363081Abstract: A fuel injection device is used in an internal combustion engine having a combustion chamber partitioned by a cylinder head, a cylinder, and a piston crown surface so that at least one of the amount of NOx, Pmax, and a thermal efficiency ? is maintained at a predetermined value. The fuel injection device includes a fuel injection change unit. The fuel injection change unit virtually divides the combustion chamber into N number of combustion zones where N is a natural number of 2 or more, and can change a fuel injection method according to the respective combustion zones. The fuel injection change unit divides the combustion chamber into the N number of combustion zones, thereby being capable of eliminating a difference of heat in the respective combustion zones, and precisely controlling an in-cylinder pressure P in the combustion chamber. As a result, the amount of NOx and the thermal efficiency can be optimized.Type: ApplicationFiled: June 7, 2016Publication date: December 15, 2016Inventors: Jun OSAKA, Kohei MOTOO, Yusuke HONGO, Kengo FURUKAWA, Wakichi KONDOH, Takamasa ITOU, Shinichiro KAWAKITA, Yoshiho UCHIYAMA, Masaki TAKEYAMA
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Publication number: 20160333763Abstract: An exhaust emission control apparatus is provided with a supply device, a catalyst, and a gas pressure reduction part. The supply device supplies a reducing agent to an exhaust passage. The catalyst purifies an exhaust gas by the use of the reducing agent. The gas pressure reduction part can make a gas pressure near the supply port lower than the gas pressure on the inside of a supply device body. A NOx catalyst adsorbs nitrogen oxide contained in the exhaust. NOx adsorbed by the NOx catalyst is desorbed from the NOx catalyst when the exhaust gas is purified. An ECU estimates an adsorption amount of NOx. Then, the ECU estimates a desorption amount of NOx desorbed from the NOx catalyst on the basis of the estimated adsorption amount of NOx.Type: ApplicationFiled: May 10, 2016Publication date: November 17, 2016Inventors: Kengo FURUKAWA, Yusuke HONGO, Jun OSAKA, Yoshiho UCHIYAMA, Takamasa ITOU, Wakichi KONDOH, Masaki TAKEYAMA, Kohei MOTOO
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Publication number: 20160043036Abstract: A conductor provided in an interconnection layer is allowed to have a low resistance. An insulator film is provided over a substrate, and is comprised of SiO(1-x)Nx (where x>0.5 in an XRD analysis result). An interconnection is provided over the insulator film, and includes a first layer and a second layer. The first layer includes at least one of TiN, TaN, WN, and RuN. The second layer is provided over the first layer, and is formed of a material having a resistance lower than the first layer, for example, W.Type: ApplicationFiled: July 24, 2015Publication date: February 11, 2016Inventors: Takashi OGURA, Tatsuya USAMI, Satoshi KODAMA, Shuuichirou UENO, Satoshi ITOU, Takamasa ITOU
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Patent number: 9136035Abstract: A flexible conductive material includes an elastomer, a conductive agent filled in the elastomer, and an adsorbent fixed inside the elastomer and able to adsorb ionic material. With the flexible conductive material, ionized impurities are unlikely to transfer to an adherend such as a dielectric film. Thus, leakage current during application of voltage decreases. Accordingly, by forming an electrode and a wiring with the flexible conductive material, leakage current can be reduced, and a transducer and a flexible wiring board having excellent durability can be produced. In addition, using the flexible conductive material, an electromagnetic shield can be produced having a small leakage current.Type: GrantFiled: June 6, 2012Date of Patent: September 15, 2015Assignee: SUMITOMO RIKO COMPANY LIMITEDInventors: Takamasa Itou, Jun Kobayashi, Hitoshi Yoshikawa
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Patent number: 8946044Abstract: A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase.Type: GrantFiled: November 29, 2012Date of Patent: February 3, 2015Assignee: Renesas Electronics CorporationInventors: Takayuki Iwaki, Takamasa Itou, Kana Shimizu
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Patent number: 8455925Abstract: To provide a structure of a semiconductor device that realizes an increase in a capacitor capacitance of a memory circuit to the maximum while inhibiting an increase in a contact resistance of a logic circuit, and a manufacture method thereof. When designating the number of layers of the local interconnect layers having wiring that makes up a logic circuit area as M and designating the number of layers of the local interconnect layers having wiring that makes up the memory circuit as N (M and N are natural numbers and satisfy M>N), capacitance elements are provided over the interconnect layers comprised of (M?N) layers or (M?N+1) layers.Type: GrantFiled: February 9, 2011Date of Patent: June 4, 2013Assignee: Renesas Electronic CoporationInventors: Masashige Moritoki, Takamasa Itou, Takashi Ogura, Tsutomu Himukai, Shigeaki Shimizu
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Patent number: 8368176Abstract: A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase.Type: GrantFiled: June 9, 2011Date of Patent: February 5, 2013Assignee: Renesas Electronics CorporationInventors: Takayuki Iwaki, Takamasa Itou, Kana Shimizu
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Publication number: 20120241689Abstract: A flexible conductive material includes an elastomer, a conductive agent filled in the elastomer, and an adsorbent fixed inside the elastomer and able to adsorb ionic material. With the flexible conductive material, ionized impurities are unlikely to transfer to an adherend such as a dielectric film. Thus, leakage current during application of voltage decreases. Accordingly, by forming an electrode and a wiring with the flexible conductive material, leakage current can be reduced, and a transducer and a flexible wiring board having excellent durability can be produced. In addition, using the flexible conductive material, an electromagnetic shield can be produced having a small leakage current.Type: ApplicationFiled: June 6, 2012Publication date: September 27, 2012Applicant: TOKAI RUBBER INDUSTRIES, LTD.Inventors: Takamasa ITOU, Jun KOBAYASHI, Hitoshi YOSHIKAWA
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Publication number: 20110304017Abstract: A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase.Type: ApplicationFiled: June 9, 2011Publication date: December 15, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takayuki IWAKI, Takamasa ITOU, Kana SHIMIZU
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Publication number: 20110193136Abstract: To provide a structure of a semiconductor device that realizes an increase in a capacitor capacitance of a memory circuit to the maximum while inhibiting an increase in a contact resistance of a logic circuit, and a manufacture method thereof. When designating the number of layers of the local interconnect layers having wiring that makes up a logic circuit area as M and designating the number of layers of the local interconnect layers having wiring that makes up the memory circuit as N (M and N are natural numbers and satisfy M>N), capacitance elements are provided over the interconnect layers comprised of (M?N) layers or (M?N+1) layers.Type: ApplicationFiled: February 9, 2011Publication date: August 11, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masashige MORITOKI, Takamasa ITOU, Takashi OGURA, Tsutomu HIMUKAI, Shigeaki SHIMIZU
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Patent number: 7786005Abstract: An increase of the via resistance resulted due to the presence of the altered layer that has been formed and grown after the formation of the via hole can be effectively prevented, thereby providing an improved reliability of the semiconductor device. A method includes: forming a TiN film on the semiconductor substrate; forming an interlayer insulating film on a surface of the TiN film; forming a resist film on a surface of the interlayer insulating film; etching the semiconductor substrate having the resist film formed thereon to form an opening, thereby partially exposing the TiN film; plasma-processing the exposed portion of the TiN film to remove an altered layer formed in the exposed portion of the TiN film; and stripping the resist film via a high temperature-plasma processing.Type: GrantFiled: March 8, 2006Date of Patent: August 31, 2010Assignee: NEC Electronics CorporationInventors: Kenichi Yamamoto, Masashige Moritoki, Takashi Shimane, Kazumi Saito, Hiroaki Tomimori, Takamasa Itou, Kousei Ushijima, Katsuro Tateyama
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Patent number: 7687918Abstract: The present invention provides a semiconductor device comprising a metal interconnect having considerably improved electromigration resistance and/or stress migration resistance. The copper interconnect 107 comprises a silicon-lower concentration region 104 and a silicon solid solution layer 106 disposed thereon. The silicon solid solution layer 106 has a structure, in which silicon atoms are introduced within the crystal lattice structure that constitutes the copper interconnect 107 to be disposed within the lattice as inter-lattice point atoms or substituted atoms. The silicon solid solution layer 106 has the structure, in which the crystal lattice structure of copper (face centered cubic lattice; lattice constant is 3.6 angstrom) remains, while silicon atoms are introduced as inter-lattice point atoms or substituted atoms.Type: GrantFiled: December 22, 2003Date of Patent: March 30, 2010Assignee: NEC Electronics CorporationInventors: Yorinobu Kunimune, Mieko Hasegawa, Takamasa Itou, Takeshi Takeda, Hidemitsu Aoki
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Patent number: 7585771Abstract: Method for manufacturing a semiconductor device, includes: forming a layer of dicobalt monosilicide (Co2Si) or of cobalt (Co) on a device-forming surface of a silicon substrate in a sputter apparatus, by utilizing a predetermined temperature profile; elevating a temperature of the silicon substrate to a predetermined temperature T2, which is equal to or higher than 600° C., conducted after forming the layer of Co or Co2Si; and forming a layer of monocobalt monosilicide (CoSi) on the device-forming surface of the silicon substrate at a temperature equal to or higher than T2, conducted after heating the silicon substrate to T2, wherein, the silicon substrate is elevated to a temperature between a highest reachable temperature T1 of the silicon substrate during forming the layer of Co or Co2Si and the temperature T2 at a temperature ramp rate of equal to or higher than 50° C./sec.Type: GrantFiled: April 24, 2006Date of Patent: September 8, 2009Assignee: NEC Electronics CorporationInventors: Tomoko Matsuda, Takamasa Itou
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Publication number: 20060240667Abstract: Method for manufacturing a semiconductor device, includes: forming a layer of dicobalt monosilicide (Co2Si) or of cobalt (Co) on a device-forming surface of a silicon substrate in a sputter apparatus, by utilizing a predetermined temperature profile; elevating a temperature of the silicon substrate to a predetermined temperature T2, which is equal to or higher than 600° C., conducted after forming the layer of Co or Co2Si; and forming a layer of monocobalt monosilicide (CoSi) on the device-forming surface of the silicon substrate at a temperature equal to or higher than T2, conducted after heating the silicon substrate to T2, wherein, the silicon substrate is elevated to a temperature between a highest reachable temperature T1 of the silicon substrate during forming the layer of Co or Co2Si and the temperature T2 at a temperature ramp rate of equal to or higher than 50° C./sec.Type: ApplicationFiled: April 24, 2006Publication date: October 26, 2006Applicant: NEC ELECTRONICS CORPORATIONInventors: Tomoko Matsuda, Takamasa Itou
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Publication number: 20060214300Abstract: An increase of the via resistance resulted due to the presence of the altered layer that has been formed and grown after the formation of the via hole can be effectively prevented, thereby providing an improved reliability of the semiconductor device. A method includes: forming a TiN film on the semiconductor substrate; forming an interlayer insulating film on a surface of the TiN film; forming a resist film on a surface of the interlayer insulating film; etching the semiconductor substrate having the resist film formed thereon to form an opening, thereby partially exposing the TiN film; plasma-processing the exposed portion of the TiN film to remove an altered layer formed in the exposed portion of the TiN film; and stripping the resist film via a high temperature-plasma processing.Type: ApplicationFiled: March 8, 2006Publication date: September 28, 2006Applicant: NEC ELECTRONICS CORPORATIONInventors: Kenichi Yamamoto, Masashige Moritoki, Takashi Shimane, Kazumi Saito, Hiroaki Tomimori, Takamasa Itou, Kousei Ushijima, Katsuro Tateyama