Patents by Inventor Takamasa Suzuki

Takamasa Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11963772
    Abstract: A system includes: a light source that emits pulsed light that illuminates a user's head portion; a photodetector that detects at least part of pulsed light returning from the head portion and that outputs one or more signals corresponding to an intensity of the at least part; electrical circuitry; and a memory that stores an emotion model indicating a relationship between the one or more signals and emotions. Based on a change in the one or more signals, the electrical circuitry selects an emotion by referring to the model. The one or more signals include a first signal corresponding to an intensity of first part of the reflection pulsed light and a second signal corresponding to an intensity of second part of the reflection pulsed light. The first part incudes part before a falling period is started; and the second part includes at least part in the falling period.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: April 23, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masato Suzuki, Takamasa Ando
  • Patent number: 11935617
    Abstract: Methods, systems, and devices for non-destructive pattern identification at a memory device are described. A memory device may perform pattern identification within the memory device and output a flag indicating whether a first data pattern matches with a second data pattern. The memory device may access one or more memory cells, via a word line, and latch the second data pattern of the memory cells to a sense amplifier. The memory device may deactivate the word line, which may result in isolating the memory cells from potential destruction of data. The memory device may write a first data pattern to the sense amplifier and compare the first data pattern and second data pattern at the sense amplifier. The memory device may output a signal indicating whether the data patterns match.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: March 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Takamasa Suzuki
  • Publication number: 20240017011
    Abstract: A device assembly for a needleless injector including a gas generating agent formed such that a combustion rate thereof is lower than a combustion rate of an ignition agent and a combustion duration thereof is longer than a combustion duration of the ignition agent. The device assembly may be configured to pressurize the injection objective substance such that an ejection pressure of the injection objective substance, defined as a pressure of the injection objective substance ejected from an ejection port, increases to a first peak pressure after pressurization is started, decreases to a pressure lower than the first peak pressure, and then increases again to a second peak pressure. The device assembly may be configured to activate an igniter and cause the ejection pressure of the injection objective substance to reach the first peak pressure by a pressure of a combustion gas of the ignition agent.
    Type: Application
    Filed: September 15, 2021
    Publication date: January 18, 2024
    Inventors: Yasunori IWAI, Takamasa SUZUKI, Yuzo YAMAMOTO
  • Patent number: 11869580
    Abstract: Apparatuses, systems, and methods for counter based read clocks in stacked memory devices. An interface die provides a read command to a core die, which reads data with timing based on the read command provides that data to a read FIFO circuit of the core die. A delay time after providing the read command, the interface die begins providing a counter-based clock signal which operates an output of the read FIFO. The counter-based clock signal operates on a different time domain (e.g., a faster frequency) than the timing of the read command.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Tomohiko Yamagishi, Seiji Narui, Kiyoshi Nakai, Takamasa Suzuki
  • Patent number: 11858088
    Abstract: A polishing apparatus includes a chuck table, a rotation mechanism that rotates the chuck table around a predetermined rotation axis, a polishing unit that has a spindle and in which a polishing pad for polishing the wafer sucked and held by the holding surface is mounted on a lower end part of the spindle, a slurry supply unit, and a cleaning unit that cleans the holding surface. The cleaning unit has a cleaning abrasive stone for removing the slurry that adheres to the holding surface through getting contact with the holding surface and a positioning unit that positions the cleaning abrasive stone to a cleaning position at which the cleaning abrasive stone gets contact with the holding surface and an evacuation position at which the cleaning abrasive stone is separate from the holding surface. Hardness of the cleaning abrasive stone is lower than the hardness of the holding surface.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: January 2, 2024
    Assignee: DISCO CORPORATION
    Inventors: Toshiyuki Moriya, Takamasa Suzuki, Yuki Inoue, Jai Kwang Han
  • Patent number: 11847142
    Abstract: There is provided a system configured to appropriately determine a topic count in accordance with LDA to estimate latent meanings of a document. For a plurality of documents d, a perplexity PPL of each document d is evaluated in accordance with a document generation probability in which the document d is generated when topic counts N for defining a topic model based on the LDA as a document generation model are hypothetically specified as different values and word groups are specified by different random numbers. The topic model is defined by a reference topic count No determined by combining a first topic count N1 (the number of topics indicating a highest cumulative frequency at which the perplexity PPL first indicates a minimum value) and a second topic count N2 (the number of topics indicating a highest cumulative frequency at which the perplexity PPL indicates a smallest value).
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: December 19, 2023
    Assignee: HONDA MOTOR CO., LTD.
    Inventor: Takamasa Suzuki
  • Publication number: 20230352075
    Abstract: Apparatuses, systems, and methods for access based refresh operations. A memory bank may be divided into multiple sub-banks, each of which has a refresh control circuit. A word line in a first sub-bank may be refreshed responsive to a word line in a second sub-bank being accessed. Once a threshold number of refreshes have been performed in the sub-bank, further accesses to the other sub-banks may be ignored. If the threshold has not been met at the end of a refresh period, then the refresh control circuit may issue a refresh signal.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 2, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Takamasa Suzuki
  • Publication number: 20230352076
    Abstract: Apparatuses, systems, and methods for access based targeted refresh operations. A memory bank has a first sub-bank and a second sub-bank. A refresh control circuit detects an aggressor in one of the sub-banks. Responsive to an access in the other sub-bank, the refresh control circuit performs a targeted refresh operation based on the sub-bank based on the aggressor address.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 2, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Yuan He, Takamasa Suzuki
  • Patent number: 11798634
    Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ki-Jun Nam, Takamasa Suzuki, Yantao Ma, Yasushi Matsubara
  • Publication number: 20230326494
    Abstract: Methods, systems, and devices for non-destructive pattern identification at a memory device are described. A memory device may perform pattern identification within the memory device and output a flag indicating whether a first data pattern matches with a second data pattern. The memory device may access one or more memory cells, via a word line, and latch the second data pattern of the memory cells to a sense amplifier. The memory device may deactivate the word line, which may result in isolating the memory cells from potential destruction of data. The memory device may write a first data pattern to the sense amplifier and compare the first data pattern and second data pattern at the sense amplifier. The memory device may output a signal indicating whether the data patterns match.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Inventors: Yuan He, Takamasa Suzuki
  • Patent number: 11772226
    Abstract: A polishing apparatus includes a holding table having a holding surface that holds a wafer, a polishing unit in which a polishing pad having an opening at the center of a polishing surface that polishes the wafer is mounted to a spindle and is rotated, a slurry supply unit that supplies slurry to the polishing surface of the polishing pad, and an air supply unit that shuts an upper end of a penetrating path penetrating through the axial center of rotation of the polishing pad and the spindle and supplies air into the penetrating path.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: October 3, 2023
    Assignee: DISCO CORPORATION
    Inventors: Yuki Inoue, Takamasa Suzuki
  • Publication number: 20230218828
    Abstract: A needleless injector includes an injector main body, a housing part including an accommodating space in which an injection substance is accommodated, the housing part defining a flow path to enable the injection substance to be ejected to a target region through an ejection port, and an attachment part configured to attach the housing part to the injector main body. The attachment part attaches the housing part to the injector main body, with a distal end side outer surface of the housing part corresponding to an inner surface of the housing part on a distal end side, where a communication portion where the flow path is in communication with the accommodating space is located, pressed in a direction opposite to a movement direction of a pressurizing unit that pressurizes the injection substance toward the ejection port.
    Type: Application
    Filed: April 14, 2021
    Publication date: July 13, 2023
    Inventor: Takamasa SUZUKI
  • Publication number: 20230215858
    Abstract: Layouts of data pads and dummy data pads are disclosed. A die may include a number of circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite the first edge, and a fourth edge. The die may further include a first number of data pads variously electrically coupled to the number of circuits and arranged proximate to the first edge and a first number of dummy data pads, not electrically coupled to the number of circuits, alternatingly arranged with the first number of data pads, and proximate to the first edge. The die may further include a second number of data pads arranged proximate to the third edge and a second number of dummy data pads, alternatingly arranged with the second number of data pads, and proximate to the third edge. Associated devices, systems, and methods are also disclosed.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Inventor: Takamasa Suzuki
  • Publication number: 20230215494
    Abstract: Apparatuses, systems, and methods for counter based read clocks in stacked memory devices. An interface die provides a read command to a core die, which reads data with timing based on the read command provides that data to a read FIFO circuit of the core die. A delay time after providing the read command, the interface die begins providing a counter-based clock signal which operates an output of the read FIFO. The counter-based clock signal operates on a different time domain (e.g., a faster frequency) than the timing of the read command.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Tomohiko Yamagishi, Seiji Narui, Kiyoshi Nakai, Takamasa Suzuki
  • Publication number: 20230215859
    Abstract: Layouts for data pads on a semiconductor die are disclosed. An apparatus may include circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite the first edge, and a fourth edge opposite the second edge. The apparatus may also include data pads variously electrically coupled to the circuits. The data pads may include a data pad positioned a first distance from the first edge and a second distance from the second edge. The apparatus may also include dummy data pads electrically isolated from the circuits. The dummy data pads may include a dummy data pad positioned substantially the first distance from the first edge and substantially the second distance from the fourth edge. Associated systems and methods are also disclosed.
    Type: Application
    Filed: August 31, 2022
    Publication date: July 6, 2023
    Inventors: Andreas Kuesel, Takamasa Suzuki
  • Publication number: 20230215828
    Abstract: Layouts for data pads on a semiconductor die are disclosed. An apparatus may include circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite the first edge, and a fourth edge opposite the second edge. The apparatus may also include data pads variously electrically coupled to the circuits. The data pads may include a data pad positioned a first distance from the first edge and a second distance from the second edge. The apparatus may also include dummy data pads electrically isolated from the circuits. The dummy data pads may include a dummy data pad positioned substantially the first distance from the first edge and substantially the second distance from the fourth edge. Associated systems and methods are also disclosed.
    Type: Application
    Filed: August 31, 2022
    Publication date: July 6, 2023
    Inventors: Andreas Kuesel, Takamasa Suzuki, Jens Polney, Seiji Narui, Shiro Uchiyama
  • Patent number: 11672911
    Abstract: A needleless injector pressurizes a substance to be injected having an ejection pressure defined as a pressure of the substance to be injected ejected through an ejection port. The ejection pressure is raised to a first peak pressure after pressurizing is started, is lowered to a pressure lower than the first peak pressure afterward, and then is raised to a second peak pressure again. An on-completion reached depth that is an on-completion reached depth of the substance when the pressurizing portion completes pressurizing is adjustable, the on-completion reached depth being increased along with increase of the first peak pressure and being increased along with reduction of a length between peaks from a first timing at which the ejection pressure reaches the first peak pressure to a second timing at which the ejection pressure reaches the second peak pressure.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 13, 2023
    Assignee: Daicel Corporation
    Inventors: Takamasa Suzuki, Shingo Atobe, Hiroshi Miyazaki, Hiromitsu Iga, Katsuya Miki
  • Patent number: 11651815
    Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: May 16, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Katsuhiro Kitagawa, Yoshihito Morishita, Daigo Toyama, Takamasa Suzuki
  • Patent number: 11646073
    Abstract: Some embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: May 9, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hyunui Lee, Takamasa Suzuki, Yasuo Satoh, Yuan He
  • Patent number: D984640
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: April 25, 2023
    Assignee: DAICEL CORPORATION
    Inventors: Takamasa Suzuki, Yuzo Yamamoto