Patents by Inventor Takamasa Suzuki

Takamasa Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220157367
    Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.
    Type: Application
    Filed: February 1, 2022
    Publication date: May 19, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Katsuhiro Kitagawa, Yoshihito Morishita, Daigo Toyama, Takamasa Suzuki
  • Patent number: 11302382
    Abstract: Apparatuses and methods for controlling driving signals are disclosed herein. Word drivers may be included in a memory device for driving hierarchical structured main word lines and subword lines. The subword lines may be driven by subword drivers that are activated by main word drivers and word drivers. In driving the word lines, driving signals are driven between an active state having an active voltage and an inactive state having an inactive voltage. The active voltage may be a voltage of a power supply and the inactive voltage may be an intermediate voltage between the active voltage and a reference voltage, such as ground. Driving the driving signals in such a manner may reduce current consumption of the memory device in some operations, for example, such as refresh operations.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Takamasa Suzuki, Nobuo Yamamoto
  • Patent number: 11276455
    Abstract: A memory device is provided. The memory device includes a memory bank configured to store data in one or more memory cells. The memory device further includes a sense amplifier and associated circuitry configured to detect a first threshold representative of a first external voltage ramping down during a power off of the memory device, and one or more switches triggered via the sense amplifier and associated circuitry to provide for a power off sequence for the memory bank based on using a second external voltage ramping down during the power off of the memory device.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Takamasa Suzuki, Yasushi Matsubara, John D. Porter, Ki-Jun Nam
  • Publication number: 20220076725
    Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.
    Type: Application
    Filed: November 11, 2021
    Publication date: March 10, 2022
    Inventors: Ki-Jun Nam, Hiroshi Akamatsu, Takamasa Suzuki, Yasushi Matsubara
  • Publication number: 20220072232
    Abstract: A needleless injector according to the present disclosure includes a housing part including an accommodating space in which an intended injection substance is accommodated. The housing part includes: a housing part main body incorporating the accommodating space; a protrusion including a distal end surface in which an ejection port is formed, the protrusion having an outer diameter that is smaller than an outer diameter of the housing part main body, the distal end surface having an outer circumference edge represented by an intersection point between a first straight line and a second straight line; and a connection part connecting the protrusion and the housing part main body to each other, and having an outer surface forming an annular inclined surface that is inclined with respect to a center axis of the housing part.
    Type: Application
    Filed: December 27, 2019
    Publication date: March 10, 2022
    Applicant: DAICEL CORPORATION
    Inventors: Takamasa SUZUKI, Takashi HASEGAWA, Shingo ATOBE, Yuzo YAMAMOTO, Hiromitsu IGA
  • Patent number: 11270758
    Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: March 8, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Katsuhiro Kitagawa, Yoshihito Morishita, Daigo Toyama, Takamasa Suzuki
  • Patent number: 11257532
    Abstract: Apparatuses and methods for driving word driver lines in a gradual manner are disclosed herein. Word driver lines may be driven to intermediate potentials between high and low potentials. In some examples, the word driver lines may be driven in a step-wise manner. In some examples, the intermediate potential may be a bias voltage. The bias voltage may be provided by a bias voltage generator. One or more enable signals may be used to control the driving of the word driver line. In some examples, an address signal may be used to control the driving of the word driver line. Driving the word driver line in a gradual manner may cause a word line to discharge in a gradual manner in some examples.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Takamasa Suzuki
  • Patent number: 11257549
    Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ki-Jun Nam, Takamasa Suzuki, Yantao Ma, Yasushi Matsubara
  • Publication number: 20220036939
    Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.
    Type: Application
    Filed: July 29, 2020
    Publication date: February 3, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Katsuhiro Kitagawa, Yoshihito Morishita, Daigo Toyama, Takamasa Suzuki
  • Publication number: 20220026370
    Abstract: In a sulfur chemiluminescence detector (SCD) including a heating furnace 210 including a combustion tube 211 and a heating means 215 for heating the combustion tube 211, an inert-gas introduction tube 214 that has the front end inserted into an end portion on an inlet side of the combustion tube 211 and has the rear end into which an end portion on the outlet side of a column 140 of a gas chromatograph is inserted, and inert-gas supplying means 264, 221, and 251 for supplying inert gas into the inert-gas introduction tube 214 in a manner that the inert gas flows from the rear end to the front end are provided. The inert gas (for example, nitrogen) flowing through the inert-gas introduction tube 214 can prevent the end portion on the outlet side of the column 140 from being exposed to oxygen. In this manner, generation of column bleeding caused by a decomposition product of the liquid phase can be suppressed, so that a decrease in the sensitivity of the SCD can be suppressed.
    Type: Application
    Filed: December 20, 2018
    Publication date: January 27, 2022
    Applicant: SHIMADZU CORPORATION
    Inventor: Takamasa SUZUKI
  • Publication number: 20220016740
    Abstract: A polishing apparatus for polishing a workpiece includes a chuck table having a holding surface for holding the workpiece placed on the holding surface under suction thereon, a polishing unit for polishing the workpiece held on the chuck table with a polishing pad while supplying a slurry to the workpiece, and a high-pressure steam ejecting unit having a nozzle for ejecting high-pressure steam to the holding surface of the chuck table. The high-pressure steam ejecting unit ejects high-pressure steam to swarf produced from polishing the workpiece and deposited on an outer circumferential portion of the holding surface for thereby removing the swarf from the holding surface.
    Type: Application
    Filed: June 15, 2021
    Publication date: January 20, 2022
    Inventors: Toshiyuki MORIYA, Takamasa SUZUKI
  • Publication number: 20220011237
    Abstract: A sulfur chemiluminescence detector includes a heating furnace 210 that includes a gas passage 211 which is a passage extending to left and right, in which an end portion on an outlet side of a column 140 of a gas chromatogram is inserted into an end portion on an inlet side, and a heating means 215 for heating the gas passage, a reaction cell 231 configured to cause gas that has passed through the gas passage to react with ozone, a photodetector 233 configured to detect light emitted from the reaction cell, a housing 240 that houses the heating furnace, the reaction cell, and the photodetector, and an interface 250 that is attached to penetrate a wall of the housing and provided with a column passage 251 through which the column 140 is inserted and a heating means 252 for heating the column passage 251.
    Type: Application
    Filed: December 12, 2018
    Publication date: January 13, 2022
    Applicant: SHIMADZU CORPORATION
    Inventor: Takamasa SUZUKI
  • Publication number: 20220000717
    Abstract: The adapter includes a housing and a filling nozzle provided in communication with a containing portion in the housing and coming into contact with an end surface of the injection device, in which the injection port of the injection nozzle is formed, when the housing is attached to the injection device. An open end of the filling nozzle is set to be smaller than an inner diameter of the containing portion and larger than the injection port. Of an internal space of the housing from a partial region of the containing portion to the open end, at least a predetermined space being continuous and including the partial region is formed in a manner where an inner diameter of the predetermined space decreases toward a side of the open end. According to this configuration, the injection fluid can be suitably transferred from the outside to a needleless injector.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 6, 2022
    Applicant: DAICEL CORPORATION
    Inventors: Yuzo YAMAMOTO, Takamasa SUZUKI
  • Publication number: 20210373648
    Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.
    Type: Application
    Filed: June 2, 2020
    Publication date: December 2, 2021
    Inventors: Ki-Jun Nam, Yantao Ma, Yasushi Matsubara, Takamasa Suzuki
  • Patent number: 11176985
    Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ki-Jun Nam, Hiroshi Akamatsu, Takamasa Suzuki, Yasushi Matsubara
  • Publication number: 20210350861
    Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 11, 2021
    Inventors: Ki-Jun Nam, Takamasa Suzuki, Yantao Ma, Yasushi Matsubara
  • Publication number: 20210263796
    Abstract: An apparatus may comprise an ECC circuit configured to receive read data from a memory cell array to correct, an error bit contained in a data portion of the read data responsive, at least in part, to a parity portion of the read data, to generate a plurality of first error determination signals and a plurality of second error determination signals. Each of the plurality of first error determination signals provided in common to n data terminals and corresponding to an associated one of burst data of m bits. Each of the plurality of second error determination signals provided in common to the burst data of m bits and corresponding to an associated one of the n data terminals. The error bit of the data portion of the read data is detected based, at least in part, on the first error determination signals and the second error determination signals.
    Type: Application
    Filed: April 23, 2021
    Publication date: August 26, 2021
    Applicant: Micron Technology, Inc.
    Inventor: Takamasa Suzuki
  • Publication number: 20210263953
    Abstract: There is provided a system configured to appropriately determine a topic count in accordance with LDA to estimate latent meanings of a document. For a plurality of documents d, a perplexity PPL of each document d is evaluated in accordance with a document generation probability in which the document d is generated when topic counts N for defining a topic model based on the LDA as a document generation model are hypothetically specified as different values and word groups are specified by different random numbers. The topic model is defined by a reference topic count N0 determined by combining a first topic count N1 (the number of topics indicating a highest cumulative frequency at which the perplexity PPL first indicates a minimum value) and a second topic count N2 (the number of topics indicating a highest cumulative frequency at which the perplexity PPL indicates a smallest value).
    Type: Application
    Filed: February 22, 2021
    Publication date: August 26, 2021
    Inventor: Takamasa SUZUKI
  • Publication number: 20210233580
    Abstract: The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can include an array of memory cells; and a controller coupled to the array configured to sense a first memory cell based upon a first input associated with the memory cell and a second input and a third input associated with a second memory cell.
    Type: Application
    Filed: April 16, 2021
    Publication date: July 29, 2021
    Inventor: Takamasa Suzuki
  • Publication number: 20210183429
    Abstract: Apparatuses and methods for controlling driving signals are disclosed herein. Word drivers may be included in a memory device for driving hierarchical structured main word lines and subword lines. The subword lines may be driven by subword drivers that are activated by main word drivers and word drivers. In driving the word lines, driving signals are driven between an active state having an active voltage and an inactive state having an inactive voltage. The active voltage may be a voltage of a power supply and the inactive voltage may be an intermediate voltage between the active voltage and a reference voltage, such as ground. Driving the driving signals in such a manner may reduce current consumption of the memory device in some operations, for example, such as refresh operations.
    Type: Application
    Filed: February 25, 2021
    Publication date: June 17, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Takamasa Suzuki, Nobuo Yamamoto