Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.

Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.

Abstract: A carbon dioxide separation membrane according to the present invention includes: an ionic liquid affinitive porous layer (C) having an ionic liquid-containing liquid (A) retained in voids; and an ionic liquid non-affinitive porous layer (B). The ionic liquid affinitive porous layer (C) may contain inorganic materials (for example, metal oxide particles having an average particle size of about 0.001 to 5 ?m on a number basis). An average thickness of the ionic liquid affinitive porous layer (C) may be about from 0.01 to 10 ?m. The ionic liquid affinitive porous layer (C) may include the ionic liquid-containing liquid (A) at a ratio from 0.1 to 99 parts by volume with respect to 100 parts by volume of voids. It may be a carbon dioxide separation membrane for fertilizing plants with carbon dioxide. The carbon dioxide separation membrane can reduce a size of the carbon dioxide concentrating device and enables smooth operation of the device.

Abstract: An apparatus and a method that provide a bias voltage to a charge pump circuit are described. An example apparatus includes: a bias voltage generator that receives a first voltage and provides a second voltage responsive to the first voltage; a charge pump circuit that receives an input signal and provides the first voltage. The charge pump circuit includes an inverter and a bias transistor. The inverter receives the input signal and provides a third voltage. The bias transistor coupled between a power node having a power supply voltage and a slew rate driver of the inverter. The bias transistor receives the second voltage and provides a power supply voltage to the slew rate driver responsive to the second voltage less than a threshold voltage and stops providing the power supply voltage to the slew rate driver responsive to the second voltage greater than the threshold voltage.

Abstract: This ionic liquid-containing laminate includes a porous layer having affinity with ionic liquids (C), said layer holding an ionic liquid-containing liquid (A) within voids therein, and a porous layer lacking affinity with ionic liquids (B). The porous layer having affinity with ionic liquids (C) may include an inorganic material (e.g., metal oxide particles having an average particle size of 0.001 to 10 ?m on a number basis). The ionic liquid-containing liquid (A) may include an ionic liquid containing cations selected from ammonium, imidazolium and phosphonium cations, and anions selected from fluorine-containing anions, cyano-containing anions and amino acid-derived anions. The porous layer having affinity with ionic liquids (C) may include 1 to 100 volume parts of the ionic liquid-containing liquid (A) with respect to 100 volume parts of voids therein.

Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.

Abstract: A polishing apparatus includes a chuck table, a rotation mechanism that rotates the chuck table around a predetermined rotation axis, a polishing unit that has a spindle and in which a polishing pad for polishing the wafer sucked and held by the holding surface is mounted on a lower end part of the spindle, a slurry supply unit, and a cleaning unit that cleans the holding surface. The cleaning unit has a cleaning abrasive stone for removing the slurry that adheres to the holding surface through getting contact with the holding surface and a positioning unit that positions the cleaning abrasive stone to a cleaning position at which the cleaning abrasive stone gets contact with the holding surface and an evacuation position at which the cleaning abrasive stone is separate from the holding surface. Hardness of the cleaning abrasive stone is lower than the hardness of the holding surface.

Abstract: Some embodiments include an integrated assembly having a memory region with memory cells and sense/access lines configured for addressing the memory cells, and having a reference-voltage-generator proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the sense/access lines. Some embodiments include an integrated assembly having a memory region with memory cells, digit lines and wordlines. Each of the memory cells is uniquely addressed with one of the wordlines in combination with one of the digit lines. The wordlines are coupled with driver circuitry and the digit lines are coupled with sensing circuitry. A reference-voltage-generator is proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the wordlines and/or includes resistive units configured substantially identically to the digit lines.

Abstract: Some embodiments include an integrated assembly having a memory region with memory cells and sense/access lines configured for addressing the memory cells, and having a reference-voltage-generator proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the sense/access lines. Some embodiments include an integrated assembly having a memory region with memory cells, digit lines and wordlines. Each of the memory cells is uniquely addressed with one of the wordlines in combination with one of the digit lines. The wordlines are coupled with driver circuitry and the digit lines are coupled with sensing circuitry. A reference-voltage-generator is proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the wordlines and/or includes resistive units configured substantially identically to the digit lines.

Abstract: An apparatus may comprise an ECC circuit configured to receive read data from a memory cell array to correct, an error bit contained in a data portion of the read data responsive, at least in part, to a parity portion of the read data, to generate a plurality of first error determination signals and a plurality of second error determination signals. Each of the plurality of first error determination signals provided in common to n data terminals and corresponding to an associated one of burst data of m bits. Each of the plurality of second error determination signals provided in common to the burst data of m bits and corresponding to an associated one of the n data terminals. The error bit of the data portion of the read data is detected based, at least in part, on the first error determination signals and the second error determination signals.

Abstract: Some embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.

Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.

Abstract: Embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.

Abstract: Embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.

Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.

Abstract: Apparatuses and methods for controlling driving signals are disclosed herein. Word drivers may be included in a memory device for driving hierarchical structured main word lines and subword lines. The subword lines may be driven by subword drivers that are activated by main word drivers and word drivers. In driving the word lines, driving signals are driven between an active state having an active voltage and an inactive state having an inactive voltage. The active voltage may be a voltage of a power supply and the inactive voltage may be an intermediate voltage between the active voltage and a reference voltage, such as ground. Driving the driving signals in such a manner may reduce current consumption of the memory device in some operations, for example, such as refresh operations.

Abstract: A memory device is provided. The memory device includes a memory bank configured to store data in one or more memory cells. The memory device further includes a sense amplifier and associated circuitry configured to detect a first threshold representative of a first external voltage ramping down during a power off of the memory device, and one or more switches triggered via the sense amplifier and associated circuitry to provide for a power off sequence for the memory bank based on using a second external voltage ramping down during the power off of the memory device.

Abstract: A needleless injector according to the present disclosure includes a housing part including an accommodating space in which an intended injection substance is accommodated. The housing part includes: a housing part main body incorporating the accommodating space; a protrusion including a distal end surface in which an ejection port is formed, the protrusion having an outer diameter that is smaller than an outer diameter of the housing part main body, the distal end surface having an outer circumference edge represented by an intersection point between a first straight line and a second straight line; and a connection part connecting the protrusion and the housing part main body to each other, and having an outer surface forming an annular inclined surface that is inclined with respect to a center axis of the housing part.

Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.

Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.