Abstract: A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a dielectric film provided between the first and the second conductive layers. The dielectric film including a fluorite-type crystal and a positive ion site includes Hf and/or Zr, and a negative ion site includes O. In the dielectric film, parameters a, b, c, p, x, y, z, u, v and w satisfy a predetermined relation. The axis length of the a-axis, b-axis and c-axis of the original unit cell is a, b, and c, respectively. An axis in a direction with no reversal symmetry is c-axis, a stacking direction of atomic planes of two kinds formed by negative ions disposed at different positions is a-axis, the remainder is b-axis. The parameters x, y, z, u, v and w are values represented using the parameter p.

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.

Abstract: A nonvolatile semiconductor memory device includes a stacked body including electrode films stacked in a first direction; a conductive pillar piercing the stacked body in the first direction; an inner insulating film, a semiconductor pillar, an intermediate insulating film, a memory layer, and an outer insulating film provided between the conductive pillar and the electrode films. The inner insulating film is provided around a side face of the conductive pillar. The semiconductor pillar is provided around a side face of the inner insulating film. The intermediate insulating film is provided around a side face of the semiconductor pillar. The memory layer is provided around a side face of the intermediate insulating film. The outer insulating film is provided around a side face of the memory layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked body including electrode films stacked in a first direction; a conductive pillar piercing the stacked body in the first direction; a inner insulating film; a semiconductor pillar; an intermediate insulating film; a memory layer; and an outer insulating film. The inner insulating film, the semiconductor pillar, the intermediate insulating film, the memory layer and the outer insulating film are provided between the conductive pillar and the electrode films. The inner insulating film is provided around a side face of the conductive pillar. The semiconductor pillar is provided around a side face of the inner insulating film. The intermediate insulating film is provided around a side face of the semiconductor pillar. The memory layer is provided around a side face of the intermediate insulating film. The outer insulating film is provided around a side face of the memory layer.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate of a first conductivity type, a pair of source and drain diffusion regions of a second conductivity type oppositely formed on a surface of the semiconductor substrate, and a stacked structure having a gate insulating film, a charge accumulation film, an interlayer insulating film and a control gate which are formed in order on a channel region of the surface of the semiconductor substrate interposed between the source and drain diffusion regions. An edge of the stacked structure in the vicinity of the source region is formed away from a junction position between the source diffusion region and the channel region.

Abstract: A NAND-type nonvolatile semiconductor memory device which suppresses write error caused by hot carriers and has improved reliability is provided. On a main plane of a semiconductor substrate, a plurality of memory cell transistors connected in series with each other, and a select gate transistor connected to an end of the plurality of memory cell transistors are arranged. A first impurity layer of a conductivity type opposite to that of the substrate is formed as a common source/drain on the semiconductor substrate between the select gate transistor and the memory cell transistor connected thereto.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate of a first conductivity type, a pair of source and drain diffusion regions of a second conductivity type oppositely formed on a surface of the semiconductor substrate, and a stacked structure having a gate insulating film, a charge accumulation film, an interlayer insulating film and a control gate which are formed in order on a channel region of the surface of the semiconductor substrate interposed between the source and drain diffusion regions. An edge of the stacked structure in the vicinity of the source region is formed away from a junction position between the source diffusion region and the channel region.

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.

Abstract: In a nonvolatile semiconductor memory device, second conductivity type source and drain regions are formed separately from each other in a first conductivity type semiconductor region on a surface thereof. A second conductivity type semiconductor region is formed in the first conductivity type semiconductor region arranged between the source and drain regions and is formed separately from the source and drain regions. A first gate insulating film is formed on the semiconductor substrate arranged between the source and drain regions. A floating gate is formed on the first gate insulating film. An intermediate gate insulating film is formed on the floating gate. A control gate is formed on the floating gate over the intermediate gate insulating film.

Abstract: A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gate electrode; a control gate electrode provided on the second gate insulation film; a source layer and a drain layer that are provided in the semiconductor substrate, the source layer and the drain layer respectively being provided either side of a channel region which is below the floating gate electrode; a source electrode that is electrically connected to the source layer; a buffer film provided on the drain layer; and a memory cell including a drain electrode electrically connected to the drain layer through the buffer film, wherein when viewing the surface of the semiconductor substrate from above, an overlapped area between the floating gate electrode and the drain layer is smaller than an overlapped area between the floating gate electrode an

Abstract: A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gate electrode; a control gate electrode provided on the second gate insulation film; a source layer and a drain layer that are provided in the semiconductor substrate, the source layer and the drain layer respectively being provided either side of a channel region which is below the floating gate electrode; a source electrode that is electrically connected to the source layer; a buffer film provided on the drain layer; and a memory cell including a drain electrode electrically connected to the drain layer through the buffer film, wherein when viewing the surface of the semiconductor substrate from above, an overlapped area between the floating gate electrode and the drain layer is smaller than an overlapped area between the floating gate electrode an

Abstract: A NAND cell unit is formed with an advanced gate forming process on a semiconductor layer of a first conductivity type, which is formed on a semiconductor substrate of the first conductivity type with an insulating film interposed therebetween. First impurity-doped layers of a second conductivity type are formed on the semiconductor layer, which serve as channel regions of the select gate transistors Bit line contact- and source line contact-use second impurity-doped layers of the first conductivity type are formed at bit line and source line contact portions, sidewalls of which are covered with an insulating film.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate of a first conductivity type, a pair of source and drain diffusion regions of a second conductivity type oppositely formed on a surface of the semiconductor substrate, and a stacked structure having a gate insulating film, a charge accumulation film, an interlayer insulating film and a control gate which are formed in order on a channel region of the surface of the semiconductor substrate interposed between the source and drain diffusion regions. An edge of the stacked structure in the vicinity of the source region is formed away from a junction position between the source diffusion region and the channel region.

Abstract: A NAND cell unit is formed with an advanced gate forming process on a semiconductor layer of a first conductivity type, which is formed on a semiconductor substrate of the first conductivity type with an insulating film interposed therebetween. First impurity-doped layers of a second conductivity type are formed on the semiconductor layer, which serve as channel regions of the select gate transistors Bit line contact- and source line contact-use second impurity-doped layers of the first conductivity type are formed at bit line and source line contact portions, sidewalls of which are covered with an insulating film.

Abstract: A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gate electrode; a control gate electrode provided on the second gate insulation film; a source layer and a drain layer that are provided in the semiconductor substrate, the source layer and the drain layer respectively being provided either side of a channel region which is below the floating gate electrode; a source electrode that is electrically connected to the source layer; a buffer film provided on the drain layer; and a memory cell including a drain electrode electrically connected to the drain layer through the buffer film, wherein when viewing the surface of the semiconductor substrate from above, an overlapped area between the floating gate electrode and the drain layer is smaller than an overlapped area between the floating gate electrode an

Abstract: A complementary field effect transistor comprises: a semiconductor substrate; an n-type field effect transistor provided on the semiconductor substrate; and a p-type field effect transistor provided on the semiconductor substrate. The n-type field effect transistor has: a first gate insulating film containing an oxide including an element selected from the group consisting of group IV metals and Lanthanoid metals, and further containing a compound of the element and a group III element; a first gate electrode provided on the first gate insulating film; and n-type source and drain regions formed on both sides of the first gate electrode.

Abstract: The semiconductor device includes a gate insulator with a three-layer stacked structure including a first insulator on a semiconductor substrate, a second insulator on the first insulator, and a third insulator on the second insulator. The first insulator is made of silicon oxide, silicon nitride, or oxinitrided silicon. The second and the third insulator contain a metal. The dielectric constant of the second insulator is higher than the square root of the product of the dielectric constants of the first and the third insulator. The present invention provides a high-speed semiconductor device, decreasing scattering of the carriers.