Patents by Inventor Takamitsu Kanazawa
Takamitsu Kanazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10236274Abstract: Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.Type: GrantFiled: May 31, 2017Date of Patent: March 19, 2019Assignee: Renesas Electronics CorporationInventors: Yukihiro Sato, Katsuhiko Funatsu, Takamitsu Kanazawa, Masahiro Koido, Hiroyoshi Taya
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Patent number: 10049968Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.Type: GrantFiled: December 29, 2017Date of Patent: August 14, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yukihiro Sato, Akira Muto, Ryo Kanda, Takamitsu Kanazawa
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Publication number: 20180138828Abstract: Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of IGBT chips are electrically connected via a high-side relay board. That is, the first semiconductor chip and the third semiconductor chip are electrically connected via a first wire, a high-side relay board and a second wire. Similarly, the third semiconductor chip on which the control circuit is formed and a second semiconductor chip of a plurality of IGBT chips are electrically connected via a low-side relay board. That is, the second semiconductor chip and the third semiconductor chip are electrically connected via the first wire, the low-side relay board and the second wire.Type: ApplicationFiled: January 11, 2018Publication date: May 17, 2018Inventors: Kuniharu MUTO, Koji BANDO, Takamitsu KANAZAWA, Ryo KANDA, Akihiro TAMURA, Hirobumi MINEGISHI
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Publication number: 20180122727Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.Type: ApplicationFiled: December 29, 2017Publication date: May 3, 2018Inventors: Yukihiro SATO, Akira MUTO, Ryo KANDA, Takamitsu KANAZAWA
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Patent number: 9906165Abstract: Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of IGBT chips are electrically connected via a high-side relay board. That is, the first semiconductor chip and the third semiconductor chip are electrically connected via a first wire, a high-side relay board and a second wire. Similarly, the third semiconductor chip on which the control circuit is formed and a second semiconductor chip of a plurality of IGBT chips are electrically connected via a low-side relay board. That is, the second semiconductor chip and the third semiconductor chip are electrically connected via the first wire, the low-side relay board and the second wire.Type: GrantFiled: June 28, 2016Date of Patent: February 27, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kuniharu Muto, Koji Bando, Takamitsu Kanazawa, Ryo Kanda, Akihiro Tamura, Hirobumi Minegishi
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Patent number: 9887151Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.Type: GrantFiled: June 6, 2016Date of Patent: February 6, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yukihiro Sato, Akira Muto, Ryo Kanda, Takamitsu Kanazawa
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Publication number: 20170263587Abstract: Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.Type: ApplicationFiled: May 31, 2017Publication date: September 14, 2017Inventors: Yukihiro SATO, Katsuhiko FUNATSU, Takamitsu KANAZAWA, Masahiro KOIDO, Hiroyoshi TAYA
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Patent number: 9698125Abstract: Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.Type: GrantFiled: September 24, 2015Date of Patent: July 4, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yukihiro Sato, Katsuhiko Funatsu, Takamitsu Kanazawa, Masahiro Koido, Hiroyoshi Taya
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Patent number: 9666518Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.Type: GrantFiled: January 31, 2017Date of Patent: May 30, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Katsuhiko Funatsu, Yukihiro Sato, Takamitsu Kanazawa, Masahiro Koido, Hiroyoshi Taya
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Publication number: 20170141086Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.Type: ApplicationFiled: January 31, 2017Publication date: May 18, 2017Inventors: Katsuhiko FUNATSU, Yukihiro SATO, Takamitsu KANAZAWA, Masahiro KOIDO, Hiroyoshi TAYA
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Patent number: 9641102Abstract: For example, a semiconductor device has a lead connected to a second portion of a chip mounting part on which a semiconductor chip to be a heat source is mounted and a lead connected to a third portion of the chip mounting part on which the semiconductor chip to be the heat source is mounted. Further, each of the leads has a protruding portion protruding from a sealing member. In this manner, it is possible to enhance a heat dissipation characteristic of the semiconductor device.Type: GrantFiled: November 16, 2015Date of Patent: May 2, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuhiro Mitamura, Koji Bando, Yukihiro Sato, Takamitsu Kanazawa
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Patent number: 9576885Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.Type: GrantFiled: September 24, 2015Date of Patent: February 21, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Katsuhiko Funatsu, Yukihiro Sato, Takamitsu Kanazawa, Masahiro Koido, Hiroyoshi Taya
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Publication number: 20170033035Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.Type: ApplicationFiled: June 6, 2016Publication date: February 2, 2017Inventors: Yukihiro SATO, Akira MUTO, Ryo KANDA, Takamitsu KANAZAWA
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Publication number: 20170033710Abstract: Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of IGBT chips are electrically connected via a high-side relay board. That is, the first semiconductor chip and the third semiconductor chip are electrically connected via a first wire, a high-side relay board and a second wire. Similarly, the third semiconductor chip on which the control circuit is formed and a second semiconductor chip of a plurality of IGBT chips are electrically connected via a low-side relay board. That is, the second semiconductor chip and the third semiconductor chip are electrically connected via the first wire, the low-side relay board and the second wire.Type: ApplicationFiled: June 28, 2016Publication date: February 2, 2017Inventors: Kuniharu MUTO, Koji BANDO, Takamitsu KANAZAWA, Ryo KANDA, Akihiro TAMURA, Hirobumi MINEGISHI
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Patent number: 9502388Abstract: Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP1 is disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.Type: GrantFiled: February 7, 2016Date of Patent: November 22, 2016Assignee: Renesas Electronics CorporationInventors: Takamitsu Kanazawa, Satoru Akiyama
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Publication number: 20160163615Abstract: For example, a semiconductor device has a lead connected to a second portion of a chip mounting part on which a semiconductor chip to be a heat source is mounted and a lead connected to a third portion of the chip mounting part on which the semiconductor chip to be the heat source is mounted. Further, each of the leads has a protruding portion protruding from a sealing member. In this manner, it is possible to enhance a heat dissipation characteristic of the semiconductor device.Type: ApplicationFiled: November 16, 2015Publication date: June 9, 2016Inventors: Kazuhiro MITAMURA, Koji BANDO, Yukihiro SATO, Takamitsu KANAZAWA
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Publication number: 20160155726Abstract: Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP1 is disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.Type: ApplicationFiled: February 7, 2016Publication date: June 2, 2016Inventors: Takamitsu Kanazawa, Satoru Akiyama
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Publication number: 20160093589Abstract: Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.Type: ApplicationFiled: September 24, 2015Publication date: March 31, 2016Inventors: Yukihiro SATO, Katsuhiko FUNATSU, Takamitsu KANAZAWA, Masahiro KOIDO, Hiroyoshi TAYA
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Publication number: 20160093594Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.Type: ApplicationFiled: September 24, 2015Publication date: March 31, 2016Inventors: Katsuhiko FUNATSU, Yukihiro SATO, Takamitsu KANAZAWA, Masahiro KOIDO, Hiroyoshi TAYA
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Patent number: 9263435Abstract: Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP1 is disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.Type: GrantFiled: September 30, 2011Date of Patent: February 16, 2016Assignee: Renesas Electronics CorporationInventors: Takamitsu Kanazawa, Satoru Akiyama