Patents by Inventor Takamitsu Kanazawa
Takamitsu Kanazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150255455Abstract: There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set to an OFF state.Type: ApplicationFiled: May 22, 2015Publication date: September 10, 2015Inventors: Takamitsu KANAZAWA, Satoru AKIYAMA
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Patent number: 9048119Abstract: There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set in an OFF state.Type: GrantFiled: June 4, 2013Date of Patent: June 2, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takamitsu Kanazawa, Satoru Akiyama
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Publication number: 20140231829Abstract: Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP1 is disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.Type: ApplicationFiled: September 30, 2011Publication date: August 21, 2014Inventors: Takamitsu Kanazawa, Satoru Akiyama
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Patent number: 8629467Abstract: A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.Type: GrantFiled: June 26, 2012Date of Patent: January 14, 2014Assignee: Renesas Electronics CorporationInventors: Takamitsu Kanazawa, Toshiyuki Hata
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Publication number: 20130335134Abstract: There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set in an OFF state.Type: ApplicationFiled: June 4, 2013Publication date: December 19, 2013Inventors: Takamitsu KANAZAWA, Satoru AKIYAMA
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Publication number: 20120267682Abstract: A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.Type: ApplicationFiled: June 26, 2012Publication date: October 25, 2012Inventors: TAKAMITSU KANAZAWA, Toshiyuki Hata
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Patent number: 8222651Abstract: A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.Type: GrantFiled: May 8, 2010Date of Patent: July 17, 2012Assignee: Renesas Electronics CorporationInventors: Takamitsu Kanazawa, Toshiyuki Hata
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Patent number: 8039954Abstract: A first semiconductor element having a junction electrode to be connected to a first node of a bidirectional switch circuit is mounted on a first metal base plate to be a heat dissipation plate, and a second semiconductor element having a junction electrode to be connected to a second node of the bidirectional switch circuit is mounted on a second metal base plate to be a heat dissipation plate. The junction electrode of the first semiconductor element has the same potential as that of the first metal base plate, and the junction electrode of the second semiconductor element has the same potential as that of the second metal base plate. Also, the respective metal base plates and non-junction electrodes of the respective semiconductor elements are connected by metal thin wires, respectively, thereby configuring the bidirectional switch circuit.Type: GrantFiled: May 4, 2010Date of Patent: October 18, 2011Assignee: Renesas Electronics CorporationInventors: Michitaka Osawa, Takamitsu Kanazawa
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Publication number: 20110242861Abstract: The present invention provides a method of improving efficiency in a full load region in a PFC power source of an active filter method by controlling a switch circuit of the PFC power source in association with an output power of the PFC power source. A pair of two switches controlling charging/discharging an inductor is provided. A MOSFET switch having a small current capacity is used as one of the switches, and an IGBT switch of a large current capacity is used as the other switch. When an output of a voltage dividing circuit for dividing voltage of an output terminal of the PFC power source is smaller than a threshold voltage, only the MOSFET switch is operated. When the output exceeds a threshold voltage, the IGBT switch is also operated.Type: ApplicationFiled: March 9, 2011Publication date: October 6, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kazuhito AYUKAWA, Nobutoshi KASAI, Kenya YAMAUCHI, Takamitsu KANAZAWA, Daisuke IIJIMA, Mamoru KITAMURA, Makoto NAKAMURA
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Publication number: 20100289127Abstract: A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.Type: ApplicationFiled: May 8, 2010Publication date: November 18, 2010Inventors: Takamitsu Kanazawa, Toshiyuki Hata
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Publication number: 20100213510Abstract: A first semiconductor element having a junction electrode to be connected to a first node of a bidirectional switch circuit is mounted on a first metal base plate to be a heat dissipation plate, and a second semiconductor element having a junction electrode to be connected to a second node of the bidirectional switch circuit is mounted on a second metal base plate to be a heat dissipation plate. The junction electrode of the first semiconductor element has the same potential as that of the first metal base plate, and the junction electrode of the second semiconductor element has the same potential as that of the second metal base plate. Also, the respective metal base plates and non-junction electrodes of the respective semiconductor elements are connected by metal thin wires, respectively, thereby configuring the bidirectional switch circuit.Type: ApplicationFiled: May 4, 2010Publication date: August 26, 2010Inventors: Michitaka OSAWA, Takamitsu KANAZAWA
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Patent number: 7750463Abstract: A first semiconductor element having a junction electrode to be connected to a first node of a bidirectional switch circuit is mounted on a first metal base plate to be a heat dissipation plate, and a second semiconductor element having a junction electrode to be connected to a second node of the bidirectional switch circuit is mounted on a second metal base plate to be a heat dissipation plate. The junction electrode of the first semiconductor element has the same potential as that of the first metal base plate, and the junction electrode of the second semiconductor element has the same potential as that of the second metal base plate. Also, the respective metal base plates and non-junction electrodes of the respective semiconductor elements are connected by metal thin wires, respectively, thereby configuring the bidirectional switch circuit.Type: GrantFiled: December 28, 2007Date of Patent: July 6, 2010Assignee: Renesas Technology Corp.Inventors: Michitaka Osawa, Takamitsu Kanazawa
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Publication number: 20090058500Abstract: A first semiconductor element having a junction electrode to be connected to a first node of a bidirectional switch circuit is mounted on a first metal base plate to be a heat dissipation plate, and a second semiconductor element having a junction electrode to be connected to a second node of the bidirectional switch circuit is mounted on a second metal base plate to be a heat dissipation plate. The junction electrode of the first semiconductor element has the same potential as that of the first metal base plate, and the junction electrode of the second semiconductor element has the same potential as that of the second metal base plate. Also, the respective metal base plates and non-junction electrodes of the respective semiconductor elements are connected by metal thin wires, respectively, thereby configuring the bidirectional switch circuit.Type: ApplicationFiled: December 28, 2007Publication date: March 5, 2009Inventors: Michitaka Osawa, Takamitsu Kanazawa
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Publication number: 20080211010Abstract: A semiconductor device includes: a package; two semiconductor chip fixing parts located adjacently to each other in the package; and first and the second semiconductor chips, each of which is fixed on the semiconductor chip fixing part and has a field effect transistor formed therein. A gate lead G1, a source lead S1, and a drain lead D2 are arranged from left to right on the first surface of the package and a drain lead D1, a source lead S2, and a gate lead G2 are arranged from left to right on the second surface. A gap between the source lead S1 and the drain lead D2 is two times a gap between the gate lead G1 and the source lead S1, and a gap between the drain lead D1 and the source lead S2 is two times a gap between the source lead S2 and the gate lead G2.Type: ApplicationFiled: February 7, 2008Publication date: September 4, 2008Inventors: Toshiyuki Hata, Takamitsu Kanazawa, Takeshi Otani
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Patent number: 7342307Abstract: A semiconductor device includes: a package; two semiconductor chip fixing parts located adjacently to each other in the package; and first and the second semiconductor chips, each of which is fixed on the semiconductor chip fixing part and has a field effect transistor formed therein. A gate lead G1, a source lead S1, and a drain lead D2 are arranged from left to right on the first surface of the package and a drain lead D1, a source lead S2, and a gate lead G2 are arranged from left to right on the second surface. A gap between the source lead S1 and the drain lead D2 is two times a gap between the gate lead G1 and the source lead S1, and a gap between the drain lead D1 and the source lead S2 is two times a gap between the source lead S2 and the gate lead G2.Type: GrantFiled: January 4, 2007Date of Patent: March 11, 2008Assignee: Renesas Technology Corp.Inventors: Toshiyuki Hata, Takamitsu Kanazawa, Takeshi Otani
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Publication number: 20070108600Abstract: A semiconductor device includes: a package; two semiconductor chip fixing parts located adjacently to each other in the package; and first and the second semiconductor chips, each of which is fixed on the semiconductor chip fixing part and has a field effect transistor formed therein. A gate lead G1, a source lead S1, and a drain lead D2 are arranged from left to right on the first surface of the package and a drain lead D1, a source lead S2, and a gate lead G2 are arranged from left to right on the second surface. A gap between the source lead S1 and the drain lead D2 is two times a gap between the gate lead G1 and the source lead S1, and a gap between the drain lead D1 and the source lead S2 is two times a gap between the source lead S2 and the gate lead G2.Type: ApplicationFiled: January 4, 2007Publication date: May 17, 2007Inventors: Toshiyuki Hata, Takamitsu Kanazawa, Takeshi Otani
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Patent number: 7173333Abstract: A semiconductor device includes: a package; two semiconductor chip fixing parts located adjacently to each other in the package; and first and the second semiconductor chips, each of which is fixed on the semiconductor chip fixing part and has a field effect transistor formed therein. A gate lead G1, a source lead S1, and a drain lead D2 are arranged from left to right on the first surface of the package and a drain lead D1, a source lead S2, and a gate lead G2 are arranged from left to right on the second surface. A gap between the source lead S1 and the drain lead D2 is two times a gap between the gate lead G1 and the source lead S1, and a gap between the drain lead D1 and the source lead S2 is two times a gap between the source lead S2 and the gate lead G2.Type: GrantFiled: October 26, 2004Date of Patent: February 6, 2007Assignee: Renesas Technology Corp.Inventors: Toshiyuki Hata, Takamitsu Kanazawa, Takeshi Otani
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Publication number: 20050121777Abstract: A semiconductor device includes: a package; two semiconductor chip fixing parts located adjacently to each other in the package; and first and the second semiconductor chips, each of which is fixed on the semiconductor chip fixing part and has a field effect transistor formed therein. A gate lead G1, a source lead S1, and a drain lead D2 are arranged from left to right on the first surface of the package and a drain lead D1, a source lead S2, and a gate lead G2 are arranged from left to right on the second surface. A gap between the source lead S1 and the drain lead D2 is two times a gap between the gate lead G1 and the source lead S1, and a gap between the drain lead D1 and the source lead S2 is two times a gap between the source lead S2 and the gate lead G2.Type: ApplicationFiled: October 26, 2004Publication date: June 9, 2005Inventors: Toshiyuki Hata, Takamitsu Kanazawa, Takeshi Otani