Abstract: In an anomaly detection method that determines whether each frame in observation data constituted by a collection of frames sent and received over a communication network system is anomalous, a difference between a data distribution of a feature amount extracted from the frame in the observation data and a data distribution for a collection of frames sent and received over the communication network system, obtained at a different timing from the observation data, is calculated. A frame having a feature amount for which the difference is predetermined value or higher is determined to be an anomalous frame. An anomaly contribution level of feature amounts extracted from the frame determined to be an anomalous frame is calculated, and an anomalous payload part, which is at least one part of the payload corresponding to the feature amount for which the anomaly contribution level is at least the predetermined value, is output.

Abstract: A cloud server includes an equipment information storage that stores equipment table information; an equipment controller that generates control information; an encapsulator that generates control notification information by encapsulating the control information and adding header information for specifying a control device as a sending destination; and a notification information sender that sends the control notification information to the control device based on the header information. Upon acquiring the control notification information from the server, the control device removes the header information from the control notification information and decapsulates to extract the control information, and sends the extracted control information to a controlled equipment.

Abstract: A cloud server includes an equipment information storage that stores equipment table information; an equipment controller that generates control information; an encapsulator that generates control notification information by encapsulating the control information and adding header information for specifying a control device as a sending destination; and a notification information sender that sends the control notification information to the control device based on the header information. Upon acquiring the control notification information from the server, the control device removes the header information from the control notification information and decapsulates to extract the control information, and sends the extracted control information to a controlled equipment.

Abstract: A method for predicting a strength of a structure modeled by an additive manufacturing method includes acquiring a material layering method including at least one of a scanning direction, a scanning pitch, a layering direction, and a layering pitch of a material, and estimating the strength of the structure by factoring in strength anisotropy attributable to the material layering method.

Abstract: A control apparatus includes a RAM, a non-volatile storage device, and a computing device. The RAM stores an object file including an unresolved symbol. The non-volatile storage device stores a control program that can be updated. The computing device controls reception of the object file, generates a symbol-resolved object file by resolving the unresolved symbol, and updates the control program by using the symbol-resolved object file. The non-volatile storage device stores a symbol table in which only a function and a global variable that are accessed by the computing device executing a program described in the object file and that are allowed to be referred to during a process of updating the control program are defined. The computing device resolves the unresolved symbol by using the symbol table.

Abstract: A method for predicting a strength of a structure modeled by an additive manufacturing method includes acquiring a material layering method including at least one of a scanning direction, a scanning pitch, a layering direction, and a layering pitch of a material, and estimating the strength of the structure by factoring in strength anisotropy attributable to the material layering method.

Abstract: A control apparatus comprises a RAM storing an object file comprising an unresolved symbol; a non-volatile storage device storing a first control program incapable of being updated and a second control program capable of being updated; and a computing device controlling reception of the object file, generating a symbol-resolved object file by resolving the unresolved symbol, and controlling a control target device by using the first control program and the second control program. The computing device updates the second control program by using the symbol-resolved object file.

Abstract: An objective is to extract, as similar functions, not only a pair of functions having the same syntax, but also a pair of functions having different syntaxes but performing similar processes. A similarity determination apparatus includes: a dependency analyzing section to get a list of dependee elements as a dependency list, from a source code including a plurality of functions, each function depending on one of the dependee elements; a similarity calculating section to calculate, based on the dependency list, similarity between the dependee elements on which two of the plurality of functions depend, as dependee similarity, and calculate, based on the calculated dependee similarity. similarity between the two functions, as depender similarity; and a similarity threshold determining section to determine that the two functions are similar to each other when the depender similarity is equal or exceeds a first threshold.

Abstract: An assertion generating system is disclosed. In an assertion generating system 207, a graphical editor 201 generates design data of a semiconductor integrated circuit by graphically editing a specification (finite state machine, process sequence) of the semiconductor integrated circuit with the use of a state transition table and a state transition figure or by editing the process sequence into a timing chart and a time series figure based on user operations, and a syntax analyzer 203 and a property extractor 204 generate a property that verifies the specification of the semiconductor integrated circuit based on the design data. The assertion generator 205 converts the property into an assertion description language 206.

Abstract: A design supporting apparatus is disclosed, including: an inputting part; a syntactic analyzing part; and a scanning and searching part. The inputting part inputs functional description data of a register transfer level. The syntactic analyzing part conducts a syntactic analysis for the functional description data and develops a parse tree. The scanning and searching part scans and searches for the parse tree being developed by the syntactic analyzing part and searches for a description representing a comparison operator having multiple bits, the comparison operator being difficult to detect a fault by test data formed by pseudo-random numbers, which are applied from a pseudo-random number generator of a logic built-in self-test.

Abstract: A method for performing scan test on a semiconductor integrated circuit including at least two blocks to be tested. The method includes isolating each of the at least two blocks to be tested exclusively from further blocks; and supplying a plurality of scan clocks having different phases each to each of the at least two blocks. In addition, a semiconductor integrated circuit includes at least two blocks to be tested, an Core Wrapper Architecture isolation unit for isolating each of the at least two blocks to be tested exclusively from further blocks, and an input terminal for inputting a plurality of scan clocks each to each of the at least two blocks, in which a Wrapper register included in the Core Wrapper Architecture is configured to be supplied selectively with one of a scan clock and a system clock for the blocks.

Abstract: An assertion generating system is disclosed. In an assertion generating system 207, a graphical editor 201 generates design data of a semiconductor integrated circuit by graphically editing a specification (finite state machine, process sequence) of the semiconductor integrated circuit with the use of a state transition table and a state transition figure or by editing the process sequence into a timing chart and a time series figure based on user operations, and a syntax analyzer 203 and a property extractor 204 generate a property that verifies the specification of the semiconductor integrated circuit based on the design data. The assertion generator 205 converts the property into an assertion description language 206.

Abstract: An image processing device includes an information extracting unit that extracts information from a physical mark attached to a scanned document, and a user identifying unit that identifies a user. The image processing device also includes a traceability-information generating unit that generates traceability information from the information extracted by the information extracting unit, and a process selecting unit that causes the user to select at least one process for the scanned document. The image processing device generates a document attached with a new physical mark that contains the traceability information according to selected process.

Abstract: A system and a method for implementing design for testability is disclosed, in that the method includes the steps of inputting function description data for defining hardware functions represented in the form independent of architecture; recognizing register variables inferable by memory elements, which are contained in the function description data; simulating events induced by affixing random numbers to the register variables; extracting control signals contained in the function description data as extracted control signals; analyzing the results of the simulation with respect to the extracted control signals; inserting test points for control signals having low toggle rates among the extracted control signals; and executing logic synthesis on the control signals having low toggle rates including the test points.

Abstract: A testability analysis system analyzes testability by evaluating controllability and observability at the level of a hardware functional description independent of architecture.

Abstract: An analysis part analyzes a description of a logic design; an extraction part extracts a part of the description of the logic design having a fan-out number beyond a predetermined value, based on the analysis; an insertion part inserts a buffer for clock tree synthesis for performing an adjustment on the part extracted by said extracting part, the adjustment being performed at a time of subsequent layout process; and a logic synthesis part performs logic synthesis on the description of the logic design obtained after the insertion performed by said inserting part.

Abstract: A design supporting apparatus is disclosed, including: an inputting part; a syntactic analyzing part; and a scanning and searching part. The inputting part inputs functional description data of a register transfer level. The syntactic analyzing part conducts a syntactic analysis for the functional description data and develops a parse tree. The scanning and searching part scans and searches for the parse tree being developed by the syntactic analyzing part and searches for a description representing a comparison operator having multiple bits, the comparison operator being difficult to detect a fault by test data formed by pseudo-random numbers, which are applied from a pseudo-random number generator of a logic built-in self-test.

Abstract: Disclosed is a method for performing scan test on a semiconductor integrated circuit including at least two blocks to be tested each capable of performing active functions. The method includes at least the steps of isolating each of the at least two blocks to be tested exclusively from further blocks; and supplying a plurality of scan clocks each to each of the at least two blocks, in which the plurality of scan clocks each have the phase different from each other.

Abstract: A system and a method for implementing design for testability is disclosed, in that the method includes the steps of inputting function description data for defining hardware functions represented in the form independent of architecture; recognizing register variables inferable by memory elements, which are contained in the function description data; simulating events induced by affixing random numbers to the register variables; extracting control signals contained in the function description data as extracted control signals; analyzing the results of the simulation with respect to the extracted control signals; inserting test points for control signals having low toggle rates among the extracted control signals; and executing logic synthesis on the control signals having low toggle rates including the test points.

Abstract: A testability analysis system analyzes testability by evaluating controllability and observability at the level of a hardware functional description independent of architecture.