Patents by Inventor Takanaga Yamazaki
Takanaga Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11327853Abstract: A multicore system according to one or more embodiments is disclosed, which may include processors that execute processing different from each other, a selector that selects one of the processors, a checker processor, a comparator that compares an external state of the processor selected by the selector with an external state of the checker processor, or compares an internal state of the processor selected by the selector with an internal state of the checker processor, and a controller that determines that the selected processor or the checker processor is abnormal in response to the external states or the internal states not matching each other based on comparison results obtained by the comparator.Type: GrantFiled: January 5, 2021Date of Patent: May 10, 2022Assignee: SANKEN ELECTRIC, LTD.Inventor: Takanaga Yamazaki
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Patent number: 11243587Abstract: A data processing device according to one or more embodiment is disclosed. The data processing device may include a first power-on reset circuit that generates a first power-on reset signal depending on power source voltage, and a processor that activates based on a first power-on reset signal generated by the first power-on reset circuit and that runs software. The processor determines if the normal first power-on reset signal is used to cause the processor to activate and run the software.Type: GrantFiled: June 26, 2019Date of Patent: February 8, 2022Assignee: SANKEN ELECTRIC CO., LTD.Inventor: Takanaga Yamazaki
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Publication number: 20210124635Abstract: A multicore system according to one or more embodiments is disclosed, which may include processors that execute processing different from each other, a selector that selects one of the processors, a checker processor, a comparator that compares an external state of the processor selected by the selector with an external state of the checker processor, or compares an internal state of the processor selected by the selector with an internal state of the checker processor, and a controller that determines that the selected processor or the checker processor is abnormal in response to the external states or the internal states doing not match each other based on comparison results obtained by the comparator.Type: ApplicationFiled: January 5, 2021Publication date: April 29, 2021Applicant: SANKEN ELECTRIC CO., LTD.Inventor: Takanaga YAMAZAKI
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Patent number: 10571993Abstract: A microcontroller unit includes: a first arithmetic processing unit, which is able to access a data bus; a second arithmetic processing unit, which includes a processor capable of accessing the data bus, and a memory. The microcontroller unit performs a data transmitting process between peripheral circuits connected to the data bus; a first arbitration circuit, which is embedded in the second arithmetic processing unit and arbitrates access to the data bus; and a second arbitration circuit, which is embedded in the second arithmetic processing unit and arbitrates access to the memory. The memory stores arithmetic processing sequences in association with event signals transmitted from the peripheral circuits, and in response to input of the event signals, the processor executes the arithmetic processing sequences corresponding to the event signals.Type: GrantFiled: March 20, 2015Date of Patent: February 25, 2020Assignee: Sanken Electric Co., LTD.Inventors: Takanaga Yamazaki, Kazuhiro Mima
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Publication number: 20200004305Abstract: A data processing device according to one or more embodiment is disclosed. The data processing device may include a first power-on reset circuit that generates a first power-on reset signal depending on power source voltage, and a processor that activates based on a first power-on reset signal generated by the first power-on reset circuit and that runs software. The processor determines if the normal first power-on reset signal is used to cause the processor to activate and run the software.Type: ApplicationFiled: June 26, 2019Publication date: January 2, 2020Applicant: SANKEN ELECTRIC CO., LTD.Inventor: Takanaga YAMAZAKI
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Patent number: 10303476Abstract: An arithmetic processor of an embodiment comprises program counter, a program memory, registers, and a decoder. Also the arithmetic processor comprises an arithmetic unit that carries out an operation using the operand and operator acquired from the registers based on a decode result by the decoder, a data memory that stores constant data and an address in association with the data, and a load unit that comprises a load data address storing unit that stores a load data address indicating an address where the constant data is stored; and an increment unit that updates the load data address stored in the load data address storing unit. The load unit loads, from the data memory, constant data corresponding to an address specified by an operand of a load instruction from the decoder, and stores the constant data in a specific one of the registers.Type: GrantFiled: June 24, 2015Date of Patent: May 28, 2019Assignee: SANKEN ELECTRIC CO., LTD.Inventors: Kazuhiro Mima, Hiroki Yukiyama, Takanaga Yamazaki
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Patent number: 10162631Abstract: A micro controller unit includes an arithmetic processing unit that executes an arithmetic processing; a peripheral circuit unit that outputs an event signal, which is a trigger for start of the arithmetic processing, based on an operation state; and a data access control unit. When an instruction to access the data designated by the first address is received from the arithmetic processing unit, the data access control unit selectively executes, depending on the event signal input from the peripheral circuit unit: a processing of instructing the data storage unit to access data designated by a first address indicating a storage location of the data on the data storage unit; and a processing of processing of converting the first address and instructing the data storage unit to access data designated by a second address, which is associated with the first address and is different from the first address.Type: GrantFiled: October 28, 2016Date of Patent: December 25, 2018Assignee: Sanken Electric Co., LTD.Inventor: Takanaga Yamazaki
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Publication number: 20180120791Abstract: A micro controller unit includes an arithmetic processing unit that executes an arithmetic processing; a peripheral circuit unit that outputs an event signal, which is a trigger for start of the arithmetic processing, based on an operation state; and a data access control unit. When an instruction to access the data designated by the first address is received from the arithmetic processing unit, the data access control unit selectively executes, depending on the event signal input from the peripheral circuit unit: a processing of instructing the data storage unit to access data designated by a first address indicating a storage location of the data on the data storage unit; and a processing of processing of converting the first address and instructing the data storage unit to access data designated by a second address, which is associated with the first address and is different from the first address.Type: ApplicationFiled: October 28, 2016Publication date: May 3, 2018Inventor: Takanaga YAMAZAKI
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Patent number: 9851947Abstract: An arithmetic processing method is provided using a binary fixed-point arithmetic processing circuit to carry out an operation of multiplicatively dividing a dividend by a divisor. The method comprises shifting the divisor by a specific number of bits when the absolute value of the divisor is within a specific range, and holding the divisor without shifting the divisor when the absolute value of the divisor is out of the specific range, acquiring an initial value of approximation calculation for the divisor that is shifted or held without being shifted, calculating a reciprocal of the divisor by performing asymptotic approximation of the acquired initial value more than once, and calculating a product of the calculated reciprocal and the dividend, and shifting the calculated product by the specific number of bits when the divisor is shifted.Type: GrantFiled: June 23, 2015Date of Patent: December 26, 2017Assignee: SANKEN ELECTRIC CO., LTD.Inventors: Hiroki Yukiyama, Kazuhiro Mima, Takanaga Yamazaki
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Patent number: 9621040Abstract: A PWM signal generator includes a delay circuit unit, which includes a plurality of delay elements connected in series, an output terminal of the delay element in a final stage among the plurality of delay elements and an input terminal of the delay element in an initial stage among the plurality of delay elements being connected to each other; a selector, which selects any one of output signals of the plurality of delay elements based on a digital value; a PWM signal output unit, which outputs a PWM signal based on the output signal selected by the selector; a delay-amount detector, which detects an amount of delay of a signal due to the delay circuit unit; and a digital value generator, which generates the digital value by correcting predetermined data based on the amount of delay detected by the delay-amount detector.Type: GrantFiled: August 20, 2015Date of Patent: April 11, 2017Assignee: Sanken Electric Co., LTD.Inventors: Kazuhiro Mima, Hiroki Yukiyama, Takanaga Yamazaki
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Publication number: 20170054365Abstract: A PWM signal generator includes a delay circuit unit, which includes a plurality of delay elements connected in series, an output terminal of the delay element in a final stage among the plurality of delay elements and an input terminal of the delay element in an initial stage among the plurality of delay elements being connected to each other; a selector, which selects any one of output signals of the plurality of delay elements based on a digital value; a PWM signal output unit, which outputs a PWM signal based on the output signal selected by the selector; a delay-amount detector, which detects an amount of delay of a signal due to the delay circuit unit; and a digital value generator, which generate the digital value by correcting predetermined data based on the amount of delay detected by the delay-amount detector.Type: ApplicationFiled: August 20, 2015Publication date: February 23, 2017Applicant: Sanken Electric Co., LTD.Inventors: Kazuhiro Mima, Hiroki Yukiyama, Takanaga Yamazaki
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Publication number: 20160274647Abstract: A microcontroller unit includes: a first arithmetic processing unit, which is able to access a data bus; a second arithmetic processing unit, which includes a processor capable of accessing the data bus, and a memory, and performs a data transmitting process between peripheral circuits connected to the data bus; a first arbitration circuit, which is embedded in the second arithmetic processing unit and arbitrates access to the data bus; and a second arbitration circuit, which is embedded in the second arithmetic processing unit and arbitrates access to the memory, wherein the memory stores arithmetic processing sequences in association with event signals transmitted from the peripheral circuits, and in response to input of the event signals, the processor executes the arithmetic processing sequences corresponding to the event signals.Type: ApplicationFiled: March 20, 2015Publication date: September 22, 2016Applicant: Sanken Electric Co., LTD.Inventors: Takanaga Yamazaki, Kazuhiro Mima
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Publication number: 20160085511Abstract: An arithmetic processing method is provided using a binary fixed-point arithmetic processing circuit to carry out an operation of multiplicatively dividing a dividend by a divisor. The method comprises shifting the divisor by a specific number of bits when the absolute value of the divisor is within a specific range, and holding the divisor without shifting the divisor when the absolute value of the divisor is out of the specific range, acquiring an initial value of approximation calculation for the divisor that is shifted or held without being shifted, calculating a reciprocal of the divisor by performing asymptotic approximation of the acquired initial value more than once, and calculating a product of the calculated reciprocal and the dividend, and shifting the calculated product by the specific number of bits when the divisor is shifted.Type: ApplicationFiled: June 23, 2015Publication date: March 24, 2016Inventors: Hiroki YUKIYAMA, Kazuhiro MIMA, Takanaga YAMAZAKI
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Publication number: 20160054999Abstract: An arithmetic processor of an embodiment comprises program counter, a program memory, registers, and a decoder. Also the arithmetic processor comprises an arithmetic unit that carries out an operation using the operand and operator acquired from the registers based on a decode result by the decoder, a data memory that stores constant data and an address in association with the data, and a load unit that comprises a load data address storing unit that stores a load data address indicating an address where the constant data is stored; and an increment unit that updates the load data address stored in the load data address storing unit. The load unit loads, from the data memory, constant data corresponding to an address specified by an operand of a load instruction from the decoder, and stores the constant data in a specific one of the registers.Type: ApplicationFiled: June 24, 2015Publication date: February 25, 2016Inventors: Kazuhiro MIMA, Hiroki YUKIYAMA, Takanaga YAMAZAKI
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Patent number: 9135007Abstract: A technology capable of reducing load on both system processing and filter operation and improving power consumption and performance is provided. In a digital signal processor, a program memory, a program counter, and a control logic circuit are provided, and a bit field of each instruction includes instruction stop flag information and bit field information. Also, the control logic circuit carries out the control in such a manner that the instruction whose instruction stop flag information is cleared is executed as is to proceed to the next instruction processing, execution of the instruction whose instruction stop flag information is set is stopped if an execution resumption trigger condition corresponding to the bit field information is not satisfied, and the instruction whose instruction stop flag information is set is executed if the execution resumption trigger condition corresponding to bit field information is satisfied, to proceed to the next instruction processing.Type: GrantFiled: July 21, 2012Date of Patent: September 15, 2015Assignee: Sanken Electric Co., Ltd.Inventor: Takanaga Yamazaki
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Patent number: 8782300Abstract: An electronic apparatus provided with a serial communication circuit achieving a baud rate adjustment with high precision is provided. For example, a bit width of each of a plurality of bits in received serial data is measured by a clock counter, and an average value of the bit width is calculated detecting its maximum value and minimum value. Moreover, for example, a maximum tolerance and a minimum tolerance are calculated as a value substantially 1.5 times the average value and a value substantially 0.5 times the average value, and determination is made as to whether or not the maximum value and the minimum value are within a range between the maximum tolerance and the minimum tolerance. If they are within the range, the corresponding average value is set in a baud rate setting register.Type: GrantFiled: December 3, 2012Date of Patent: July 15, 2014Assignee: Sanken Electric Co., Ltd.Inventors: Ayumi Hiromatsu, Masahiro Katayama, Takanaga Yamazaki
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Publication number: 20130024673Abstract: A technology capable of reducing load on both system processing and filter operation and improving power consumption and performance is provided. In a digital signal processor, a program memory, a program counter, and a control logic circuit are provided, and a bit field of each instruction includes instruction stop flag information and bit field information. Also, the control logic circuit carries out the control in such a manner that the instruction whose instruction stop flag information is cleared is executed as is to proceed to the next instruction processing, execution of the instruction whose instruction stop flag information is set is stopped if an execution resumption trigger condition corresponding to the bit field information is not satisfied, and the instruction whose instruction stop flag information is set is executed if the execution resumption trigger condition corresponding to bit field information is satisfied, to proceed to the next instruction processing.Type: ApplicationFiled: July 21, 2012Publication date: January 24, 2013Inventor: Takanaga YAMAZAKI
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Publication number: 20100191934Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.Type: ApplicationFiled: March 18, 2010Publication date: July 29, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Patent number: 7676651Abstract: The invention provides a code compression technology that is favorable for a micro controller or other embedded system, and for compressed codes, resulting from conversion of program codes into variable length codes, and grouped program codes, address conversion information for specifying the start address of each group and compressed code type information for specifying the code length of each compressed code contained in a group are stored in a memory, and by enabling a corresponding compressed code address to be calculated from a code address output by a CPU, code compression that is favorable for a micro controller or other embedded system is realized.Type: GrantFiled: June 30, 2003Date of Patent: March 9, 2010Assignee: Hitachi, Ltd.Inventors: Hiromichi Yamada, Yuichi Abe, Yasuhiro Nakatsuka, Takanaga Yamazaki
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Publication number: 20080313444Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.Type: ApplicationFiled: August 21, 2008Publication date: December 18, 2008Inventors: Shumpei KAWASAKI, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe