Abstract: A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: A branch instruction format has different respective field lengths for conditional branch instructions and unconditional branch instructions. A conditional branch instruction has a first bit length and a first area for a displacement designating an address to be jumped, wherein the first area has a second bit length that is smaller than the first bit length. An unconditional branch instruction also has the first bit length, and a second area for a displacement designating an address to be jumped, wherein the second area has a third bit length that is different from the first and second bit lengths.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A division method and circuit performs a division for signed data by adding or subtracting a divisor to or from the dividend or the partial remainder from the division, according to the sign of the divisor or the dividend and the partial remainder to acquire a new partial remainder. The division is repeated a predetermined number of times in which a quotient bit is acquired according to the sign of the acquired partial remainder or the divisor. The dividend is corrected by subtracting 1, which is the significance of an LSB of the corresponding dividend, from the dividend when the sign of the dividend is negative, and the corrected dividend is used for the division processing.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A single chip microcomputer formed on a semiconductor substrate includes a central processing unit, a ROM storing therein a program for operating the central processing unit, a digital signal processor, and a multi-port RAM. The digital signal processor develops an outline font on the multi-port RAM in accordance with a program stored in a storage unit provided in the digital signal processor. This eliminates the necessity of development of an outline font by the central processing unit and allows high speed execution of such development of an outline font. Further, the central processing unit and the digital signal processor can operate in a parallel relationship.

Abstract: The pattern drawing system consists of a first data processor which develops the outline font data, calculates the coordinates of the points on the profile of a pattern and, according to the calculated profile coordinates, draws the profile of the pattern; and a second data processor which paints the interior of the profile drawn by the first data processor concurrently with the calculation of the profile coordinates by the first data processor. This configuration allows the first data processor to calculate the profile coordinates of a desired pattern while the second data processor is doing the painting. Such parallel operations improve the efficiency of the pattern drawing that uses the outline font data.