Patents by Inventor Takanobu Naruse

Takanobu Naruse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10734314
    Abstract: Input and output terminals are arranged so as to be adapted for an environment in which they are to be used. A semiconductor module (5) is surface-mounted on a surface wiring layer (30a) of a main substrate (3). A first module terminal group (11) located on a module first side (2a) of the semiconductor module (5) and a first substrate terminal group (301) located on a substrate first side (3a) of the main substrate (3) are connected by a first surface wiring pattern (311) formed in a surface wiring layer (30a). A second module terminal group (12) located on a module second side (2c) and a second substrate terminal group (302) located on a substrate second side (3c) are connected by a second surface wiring pattern (312) formed in the surface wiring layer (30a).
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: August 4, 2020
    Assignee: AISIN AW CO., LTD.
    Inventor: Takanobu Naruse
  • Patent number: 10707159
    Abstract: Provided is a semiconductor device having a surface layer power supply path in a surface layer wiring layer, on which a chip module is mounted, of a main substrate that has a plurality of wiring layers and through holes, the surface layer power supply path supplying power to a semiconductor chip via an inner peripheral-side power supply terminal group and an outer peripheral-side power supply terminal group. The surface layer power supply path overlaps the inner peripheral-side power supply terminal group and the outer peripheral-side power supply terminal group as seen in the orthogonal direction, and is formed continuously so as to extend in a direction from a position at which the surface layer power supply path is connected to the inner peripheral-side power supply terminal group toward the outer peripheral side of the main substrate.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 7, 2020
    Assignee: AISIN AW CO., LTD.
    Inventor: Takanobu Naruse
  • Publication number: 20200187370
    Abstract: A circuit board is installed with a semiconductor module on an upper face and provided with connection terminals on a lower face. A connection pin is provided on at least some of the connection terminals. The connection terminals include a drive terminal for driving the semiconductor module and a function terminal for connecting the semiconductor module and other function units. The disposition of the drive terminal in each of divided areas is point-symmetric with respect to a center of the circuit board. The divided areas divide the circuit board into fourths.
    Type: Application
    Filed: September 21, 2018
    Publication date: June 11, 2020
    Applicant: AISIN AW CO., LTD.
    Inventor: Takanobu NARUSE
  • Patent number: 10438637
    Abstract: There is provided a technique that makes it possible to ascertain a strobe point for data while a memory is in operation with actual data. A memory controller 1 includes a data skew adjustment part 2 that adjusts a data skew of a read data signal, a strobe adjustment part 3 that adjusts a strobe point, a data change point detection part 4 that detects a data change point, a strobe point detection part 5 that detects a strobe point, a dynamic timing calculation part 6 that calculates dynamic timing information for each read data signal, a dynamic timing information storage part 7 that stores the dynamic timing information, and a dynamic timing information output part 8 that outputs the dynamic timing information.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: October 8, 2019
    Assignee: AISIN A W CO., LTD.
    Inventor: Takanobu Naruse
  • Publication number: 20180366168
    Abstract: There is provided a technique that makes it possible to ascertain a strobe point for data while a memory is in operation with actual data. A memory controller 1 includes a data skew adjustment part 2 that adjusts a data skew of a read data signal, a strobe adjustment part 3 that adjusts a strobe point, a data change point detection part 4 that detects a data change point, a strobe point detection part 5 that detects a strobe point, a dynamic timing calculation part 6 that calculates dynamic timing information for each read data signal, a dynamic timing information storage part 7 that stores the dynamic timing information, and a dynamic timing information output part 8 that outputs the dynamic timing information.
    Type: Application
    Filed: January 24, 2017
    Publication date: December 20, 2018
    Applicant: AISIN AW CO., LTD.
    Inventor: Takanobu NARUSE
  • Publication number: 20180204819
    Abstract: Input and output terminals are arranged so as to be adapted for an environment in which they are to be used. A semiconductor module (5) is surface-mounted on a surface wiring layer (30a) of a main substrate (3). A first module terminal group (11) located on a module first side (2a) of the semiconductor module (5) and a first substrate terminal group (301) located on a substrate first side (3a) of the main substrate (3) are connected by a first surface wiring pattern (311) formed in a surface wiring layer (30a). A second module terminal group (12) located on a module second side (2c) and a second substrate terminal group (302) located on a substrate second side (3c) are connected by a second surface wiring pattern (312) formed in the surface wiring layer (30a).
    Type: Application
    Filed: August 31, 2016
    Publication date: July 19, 2018
    Applicant: AISIN AW CO., LTD.
    Inventor: Takanobu NARUSE
  • Publication number: 20180197801
    Abstract: Provided is a semiconductor device having a surface layer power supply path in a surface layer wiring layer, on which a chip module is mounted, of a main substrate that has a plurality of wiring layers and through holes, the surface layer power supply path supplying power to a semiconductor chip via an inner peripheral-side power supply terminal group and an outer peripheral-side power supply terminal group. The surface layer power supply path overlaps the inner peripheral-side power supply terminal group and the outer peripheral-side power supply terminal group as seen in the orthogonal direction, and is formed continuously so as to extend in a direction from a position at which the surface layer power supply path is connected to the inner peripheral-side power supply terminal group toward the outer peripheral side of the main substrate.
    Type: Application
    Filed: August 31, 2016
    Publication date: July 12, 2018
    Applicant: AISIN AW CO., LTD.
    Inventor: Takanobu NARUSE
  • Publication number: 20180052784
    Abstract: A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first memory interface, a second memory controller configured to output a second control signal to the second external memory through a second memory interface, an inter-device interface for communicating with another semiconductor device, terminals configured to output the second control signal that has passed through the second memory interface, and a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode of the semiconductor device and to couple the selected interface to the terminals.
    Type: Application
    Filed: October 27, 2017
    Publication date: February 22, 2018
    Inventors: Kenichiro OMURA, Ryohei YOSHIDA, Takanobu NARUSE, Seiichi SAITO
  • Publication number: 20180024747
    Abstract: A memory controller that suppresses noise generated when data is transferred to a memory, includes a write part portion that writes transmission data into the memory, and a read portion that reads data from the memory. The write portion includes a substitution unit that substitutes, when a linear sequence of a bit of “1” and a bit of “0” of a bit string configuring data transmitted through the signal line is a target pattern set as a substitution target, a substitutional bit string that suppresses noise for the bit string, before the transmission data is written into the memory. The read portion includes a restoration unit that restores a substitutional bit string read from the memory to an initial bit string.
    Type: Application
    Filed: March 24, 2016
    Publication date: January 25, 2018
    Applicant: AISIN AW CO., LTD.
    Inventor: Takanobu NARUSE
  • Patent number: 9830281
    Abstract: A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first memory interface, a second memory controller configured to output a second control signal to the second external memory through a second memory interface, an inter-device interface for communicating with another semiconductor device, terminals configured to output the second control signal that has passed through the second memory interface, and a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode of the semiconductor device and to couple the selected interface to the terminals.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: November 28, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichiro Omura, Ryohei Yoshida, Takanobu Naruse, Seiichi Saito
  • Patent number: 9647654
    Abstract: A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: May 9, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Tadashi Kameyama, Takanobu Naruse, Yohei Akita, Hirotaka Hara
  • Publication number: 20160282202
    Abstract: To suppress an increase in the number of voltage comparators with an expansion in a chip temperature detection range, a temperature sensor in a semiconductor device includes a temperature detection circuit for outputting a voltage according to the chip temperature, a reference voltage generating circuit for generating a plurality of reference voltages, and a plurality of voltage comparators for comparing each reference voltage obtained by the reference voltage generating circuit with an output voltage of the temperature detection circuit and thereby generating a chip temperature detection signal configured with multiple bits. Further, the temperature sensor includes a control circuit for controlling the reference voltages generated by the reference voltage generating circuit based on the chip temperature detection signal and thereby changing correspondence between the chip temperature detection signal and the chip temperature to shift a chip temperature detection range.
    Type: Application
    Filed: June 9, 2016
    Publication date: September 29, 2016
    Inventors: Tadashi KAMEYAMA, Takanobu NARUSE, Takayasu ITO
  • Patent number: 9389127
    Abstract: A temperature sensor in a semiconductor device includes a temperature detection circuit for outputting a voltage according to the chip temperature, a reference voltage generating circuit for generating a plurality of reference voltages, and a plurality of voltage comparators for comparing each reference voltage with an output voltage of the temperature detection circuit and thereby generating a chip temperature detection signal configured with multiple bits. Further, the temperature sensor includes a control circuit for controlling the reference voltages generated by the reference voltage generating circuit based on the chip temperature detection signal and thereby changing correspondence between the chip temperature detection signal and the chip temperature to shift a chip temperature detection range.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: July 12, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Tadashi Kameyama, Takanobu Naruse, Takayasu Ito
  • Publication number: 20160006424
    Abstract: A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result.
    Type: Application
    Filed: September 11, 2015
    Publication date: January 7, 2016
    Inventors: Tadashi Kameyama, Takanobu Naruse, Yohei Akita, Hirotaka Hara
  • Publication number: 20150311904
    Abstract: A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.
    Type: Application
    Filed: June 10, 2015
    Publication date: October 29, 2015
    Inventors: Hajime Sasaki, Hirohiko Ito, Shikiko Nachi, Takanobu Naruse
  • Patent number: 9146598
    Abstract: A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: September 29, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Tadashi Kameyama, Takanobu Naruse, Yohei Akita, Hirotaka Hara
  • Patent number: 9083353
    Abstract: A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.
    Type: Grant
    Filed: July 27, 2013
    Date of Patent: July 14, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hajime Sasaki, Hirohiko Ito, Shikiko Nachi, Takanobu Naruse
  • Publication number: 20140210544
    Abstract: A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result.
    Type: Application
    Filed: January 28, 2014
    Publication date: July 31, 2014
    Applicant: Renesas Mobile Corporation
    Inventors: TADASHI KAMEYAMA, TAKANOBU NARUSE, YOHEI AKITA, HIROTAKA HARA
  • Publication number: 20140189259
    Abstract: A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first memory interface, a second memory controller configured to output a second control signal to the second external memory through a second memory interface, an inter-device interface for communicating with another semiconductor device, terminals configured to output the second control signal that has passed through the second memory interface, and a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode of the semiconductor device and to couple the selected interface to the terminals.
    Type: Application
    Filed: November 19, 2013
    Publication date: July 3, 2014
    Applicant: Renesas Mobile Corporation
    Inventors: Kenichiro Omura, Ryohei Yoshida, Takanobu Naruse, Seiichi Saito
  • Patent number: 8659927
    Abstract: In a wiring substrate, a double data rate (DDR) memory and a memory controller controlling the DDR memory are mounted. Further, in the wiring substrate, plural equal-length wires connecting the DDR memory and the memory controller are formed. The plural equal-length wires include a differential transmission line, such as a clock wire transmitting a clock signal, which is connected via a common mode choke coil. The differential transmission line may have a wire length shorter than a wire length of another equal-length wire, by a wire length corresponding to delay time of a transmission signal due to the common mode choke coil.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: February 25, 2014
    Assignees: Murata Manufacturing Co., Ltd, Renesas Electronics Corporation
    Inventors: Takashi Ichimura, Takanobu Naruse, Chiaki Fujii