Patents by Inventor Takanobu Naruse

Takanobu Naruse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11915987
    Abstract: A semiconductor device including a power supply circuit to supply power to a circuit formed on a main substrate equipped with a circuit module is made smaller in size. A semiconductor device includes: a circuit module including a module substrate and a circuit element mounted on the module substrate; and a main substrate on which the circuit module is mounted. The semiconductor device further includes a power supply circuit to supply power to at least a circuit formed on the module substrate. The power supply circuit includes: a voltage generating circuit to output a predetermined output voltage; a first capacitor; and a second capacitor larger in capacity than the first capacitor. The voltage generating circuit and the first capacitor are mounted on the module substrate. The second capacitor is mounted on the main substrate.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: February 27, 2024
    Assignee: AISIN CORPORATION
    Inventor: Takanobu Naruse
  • Patent number: 11848251
    Abstract: A semiconductor device (1) includes a semiconductor module (20) and a fan device (30). The semiconductor module (20) includes a module board (21), a first element (22) mounted on the module board (21), and a second element (23a) having a smaller heat generation amount and lower heat resistance. In a flowing direction of an air flow (F) formed by driving the fan device (30), the fan device (30) is disposed downstream of the first element (22) and the second element (23a), and the first element (22) is disposed downstream of the second element (23a).
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 19, 2023
    Assignee: AISIN CORPORATION
    Inventors: Takanobu Naruse, Hiroyoshi Araki
  • Patent number: 11769720
    Abstract: An electronic substrate connects to a semiconductor component via a plurality of front surface terminals disposed in an array on a front surface and connects to a main substrate via a plurality of back surface terminals disposed in an array on a back surface. The electronic substrate includes: a first wiring that electrically connects the front surface terminals and the back surface terminals in the electronic substrate and is supplied with power supply from the main substrate via the back surface terminals; and a second wiring that electrically connects the front surface terminals and the back surface terminals in the electronic substrate, is supplied with power supply having the same potential as the first wiring from the main substrate via the back surface terminals, and is not electrically connected to the first wiring in the electronic substrate.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 26, 2023
    Assignee: AISIN CORPORATION
    Inventors: Takanobu Naruse, Yasuhiro Sassa
  • Publication number: 20220157362
    Abstract: A semiconductor storage device including a first magnetoresistive memory and a second magnetoresistive memory that are two types of magnetoresistive memories accessed by a target logic unit that is one logic unit. The target logic unit ? the first magnetoresistive memory, and the second magnetoresistive memory are formed on one semiconductor chip, and the first magnetoresistive memory has a larger coercive force than the second magnetoresistive memory.
    Type: Application
    Filed: December 11, 2019
    Publication date: May 19, 2022
    Applicant: AISIN CORPORATION
    Inventor: Takanobu NARUSE
  • Patent number: 11335633
    Abstract: Provided is a circuit module including a power supply chip module, a load chip module, and a system board. A power supply output terminal group of the power supply chip module is arranged side by side in a row along a side of the power supply chip module board, the power supply input terminal group of a load chip module includes a specific terminal group arranged in a specific row that is a row along a side of the load chip module board, and a wiring width along an arrangement direction of the power supply output terminal group of a wiring pattern in which the power supply output terminal group is connected to the system board is equal to or more than a wiring width W31 along an arrangement direction of the specific terminal group of the wiring pattern in which the specific terminal group is connected to the system board.
    Type: Grant
    Filed: May 27, 2019
    Date of Patent: May 17, 2022
    Assignee: AISIN CORPORATION
    Inventors: Takashi Kusano, Takanobu Naruse
  • Patent number: 11324131
    Abstract: A circuit board is installed with a semiconductor module on an upper face and provided with connection terminals on a lower face. A connection pin is provided on at least some of the connection terminals. The connection terminals include a drive terminal for driving the semiconductor module and a function terminal for connecting the semiconductor module and other function units. The disposition of the drive terminal in each of divided areas is point-symmetric with respect to a center of the circuit board. The divided areas divide the circuit board into fourths.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 3, 2022
    Assignee: AISIN CORPORATION
    Inventor: Takanobu Naruse
  • Publication number: 20220122954
    Abstract: The present invention supplies electric power to a semiconductor module appropriately and also curbs the number of wiring layers of a main substrate on which the semiconductor module is mounted. A semiconductor device (10) is provided with a main substrate (90) and a semiconductor module (1). A first power supply circuit (71), the semiconductor module (1), and a first element (9) are mounted on the main substrate (90). The semiconductor module (1) is provided with a second element (2, 3) and a module substrate (4) on which the second element (2, 3) is mounted. The first power supply circuit (71) supplies electric power (Vcc) to the first element (9). The semiconductor module (1) is further provided with a second power supply circuit (72) mounted on the module substrate (4), and the second power supply circuit (72) supplies electric power (Vcc) to the second element (2, 3).
    Type: Application
    Filed: September 12, 2019
    Publication date: April 21, 2022
    Applicant: AISIN CORPORATION
    Inventor: Takanobu NARUSE
  • Publication number: 20220108944
    Abstract: Provided is a technique that enables a passive component to be arranged with a short wiring distance to a power terminal of a semiconductor element mounted on a semiconductor module. In a semiconductor module, a plurality of first connection terminal groups having connection terminals arranged with a first gap therebetween, and a second connection terminal group having connection terminals arranged with a second gap therebetween in a rectangular ring so as to surround the first connection terminal groups, are arranged with a second group gap therebetween that is wider than the first gap and the second gap. In a plan view, a first power terminal of a first semiconductor element overlaps a target terminal group that is one of the first connection terminal groups. In the plan view, a second power terminal of a second semiconductor element overlaps the second connection terminal group.
    Type: Application
    Filed: November 21, 2019
    Publication date: April 7, 2022
    Applicant: AISIN CORPORATION
    Inventor: Takanobu NARUSE
  • Publication number: 20220084929
    Abstract: An electronic substrate connects to a semiconductor component via a plurality of front surface terminals disposed in an array on a front surface and connects to a main substrate via a plurality of back surface terminals disposed in an array on a back surface. The electronic substrate includes: a first wiring that electrically connects the front surface terminals and the back surface terminals in the electronic substrate and is supplied with power supply from the main substrate via the back surface terminals; and a second wiring that electrically connects the front surface terminals and the back surface terminals in the electronic substrate, is supplied with power supply having the same potential as the first wiring from the main substrate via the back surface terminals, and is not electrically connected to the first wiring in the electronic substrate.
    Type: Application
    Filed: October 31, 2019
    Publication date: March 17, 2022
    Applicant: AISIN CORPORATION
    Inventors: Takanobu NARUSE, Yasuhiro SASSA
  • Publication number: 20220068734
    Abstract: A semiconductor device including a power supply circuit to supply power to a circuit formed on a main substrate equipped with a circuit module is made smaller in size. A semiconductor device includes: a circuit module including a module substrate and a circuit element mounted on the module substrate; and a main substrate on which the circuit module is mounted. The semiconductor device further includes a power supply circuit to supply power to at least a circuit formed on the module substrate. The power supply circuit includes: a voltage generating circuit to output a predetermined output voltage; a first capacitor; and a second capacitor larger in capacity than the first capacitor. The voltage generating circuit and the first capacitor are mounted on the module substrate. The second capacitor is mounted on the main substrate.
    Type: Application
    Filed: December 4, 2019
    Publication date: March 3, 2022
    Applicant: AISIN CORPORATION
    Inventor: Takanobu NARUSE
  • Publication number: 20220028828
    Abstract: Connection terminals of a semiconductor module are disposed appropriately in accordance with the connection destination of the semiconductor module. A semiconductor module which includes at least one semiconductor element is mounted on a first surface of a main substrate, which has the first surface on which a first circuit element is mounted and a second surface on which a second circuit element is mounted. A plurality of connection terminals include a first connection terminal group composed of a plurality of first connection terminals to be connected to the first circuit element via the main substrate, and a second connection terminal group composed of a plurality of second connection terminals to be connected to the second circuit element via the main substrate. The first connection terminal group is disposed on the outer peripheral side with respect to the second connection terminal group.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 27, 2022
    Applicant: AISIN CORPORATION
    Inventor: Takanobu NARUSE
  • Publication number: 20220028755
    Abstract: A semiconductor device (1) includes a semiconductor module (20) and a fan device (30). The semiconductor module (20) includes a module board (21), a first element (22) mounted on the module board (21), and a second element (23a) having a smaller heat generation amount and lower heat resistance. In a flowing direction of an air flow (F) formed by driving the fan device (30), the fan device (30) is disposed downstream of the first element (22) and the second element (23a), and the first element (22) is disposed downstream of the second element (23a).
    Type: Application
    Filed: December 11, 2019
    Publication date: January 27, 2022
    Applicant: AISIN CORPORATION
    Inventors: Takanobu NARUSE, Hiroyoshi ARAKI
  • Publication number: 20210249344
    Abstract: Provided is a circuit module including a power supply chip module, a load chip module, and a system board. A power supply output terminal group of the power supply chip module is arranged side by side in a row along a side of the power supply chip module board, the power supply input terminal group of a load chip module includes a specific terminal group arranged in a specific row that is a row along a side of the load chip module board, and a wiring width along an arrangement direction of the power supply output terminal group of a wiring pattern in which the power supply output terminal group is connected to the system board is equal to or more than a wiring width W31 along an arrangement direction of the specific terminal group of the wiring pattern in which the specific terminal group is connected to the system board.
    Type: Application
    Filed: May 27, 2019
    Publication date: August 12, 2021
    Applicant: AISIN AW CO., LTD.
    Inventors: Takashi KUSANO, Takanobu NARUSE
  • Patent number: 10734314
    Abstract: Input and output terminals are arranged so as to be adapted for an environment in which they are to be used. A semiconductor module (5) is surface-mounted on a surface wiring layer (30a) of a main substrate (3). A first module terminal group (11) located on a module first side (2a) of the semiconductor module (5) and a first substrate terminal group (301) located on a substrate first side (3a) of the main substrate (3) are connected by a first surface wiring pattern (311) formed in a surface wiring layer (30a). A second module terminal group (12) located on a module second side (2c) and a second substrate terminal group (302) located on a substrate second side (3c) are connected by a second surface wiring pattern (312) formed in the surface wiring layer (30a).
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: August 4, 2020
    Assignee: AISIN AW CO., LTD.
    Inventor: Takanobu Naruse
  • Patent number: 10707159
    Abstract: Provided is a semiconductor device having a surface layer power supply path in a surface layer wiring layer, on which a chip module is mounted, of a main substrate that has a plurality of wiring layers and through holes, the surface layer power supply path supplying power to a semiconductor chip via an inner peripheral-side power supply terminal group and an outer peripheral-side power supply terminal group. The surface layer power supply path overlaps the inner peripheral-side power supply terminal group and the outer peripheral-side power supply terminal group as seen in the orthogonal direction, and is formed continuously so as to extend in a direction from a position at which the surface layer power supply path is connected to the inner peripheral-side power supply terminal group toward the outer peripheral side of the main substrate.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 7, 2020
    Assignee: AISIN AW CO., LTD.
    Inventor: Takanobu Naruse
  • Publication number: 20200187370
    Abstract: A circuit board is installed with a semiconductor module on an upper face and provided with connection terminals on a lower face. A connection pin is provided on at least some of the connection terminals. The connection terminals include a drive terminal for driving the semiconductor module and a function terminal for connecting the semiconductor module and other function units. The disposition of the drive terminal in each of divided areas is point-symmetric with respect to a center of the circuit board. The divided areas divide the circuit board into fourths.
    Type: Application
    Filed: September 21, 2018
    Publication date: June 11, 2020
    Applicant: AISIN AW CO., LTD.
    Inventor: Takanobu NARUSE
  • Patent number: 10438637
    Abstract: There is provided a technique that makes it possible to ascertain a strobe point for data while a memory is in operation with actual data. A memory controller 1 includes a data skew adjustment part 2 that adjusts a data skew of a read data signal, a strobe adjustment part 3 that adjusts a strobe point, a data change point detection part 4 that detects a data change point, a strobe point detection part 5 that detects a strobe point, a dynamic timing calculation part 6 that calculates dynamic timing information for each read data signal, a dynamic timing information storage part 7 that stores the dynamic timing information, and a dynamic timing information output part 8 that outputs the dynamic timing information.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: October 8, 2019
    Assignee: AISIN A W CO., LTD.
    Inventor: Takanobu Naruse
  • Publication number: 20180366168
    Abstract: There is provided a technique that makes it possible to ascertain a strobe point for data while a memory is in operation with actual data. A memory controller 1 includes a data skew adjustment part 2 that adjusts a data skew of a read data signal, a strobe adjustment part 3 that adjusts a strobe point, a data change point detection part 4 that detects a data change point, a strobe point detection part 5 that detects a strobe point, a dynamic timing calculation part 6 that calculates dynamic timing information for each read data signal, a dynamic timing information storage part 7 that stores the dynamic timing information, and a dynamic timing information output part 8 that outputs the dynamic timing information.
    Type: Application
    Filed: January 24, 2017
    Publication date: December 20, 2018
    Applicant: AISIN AW CO., LTD.
    Inventor: Takanobu NARUSE
  • Publication number: 20180204819
    Abstract: Input and output terminals are arranged so as to be adapted for an environment in which they are to be used. A semiconductor module (5) is surface-mounted on a surface wiring layer (30a) of a main substrate (3). A first module terminal group (11) located on a module first side (2a) of the semiconductor module (5) and a first substrate terminal group (301) located on a substrate first side (3a) of the main substrate (3) are connected by a first surface wiring pattern (311) formed in a surface wiring layer (30a). A second module terminal group (12) located on a module second side (2c) and a second substrate terminal group (302) located on a substrate second side (3c) are connected by a second surface wiring pattern (312) formed in the surface wiring layer (30a).
    Type: Application
    Filed: August 31, 2016
    Publication date: July 19, 2018
    Applicant: AISIN AW CO., LTD.
    Inventor: Takanobu NARUSE
  • Publication number: 20180197801
    Abstract: Provided is a semiconductor device having a surface layer power supply path in a surface layer wiring layer, on which a chip module is mounted, of a main substrate that has a plurality of wiring layers and through holes, the surface layer power supply path supplying power to a semiconductor chip via an inner peripheral-side power supply terminal group and an outer peripheral-side power supply terminal group. The surface layer power supply path overlaps the inner peripheral-side power supply terminal group and the outer peripheral-side power supply terminal group as seen in the orthogonal direction, and is formed continuously so as to extend in a direction from a position at which the surface layer power supply path is connected to the inner peripheral-side power supply terminal group toward the outer peripheral side of the main substrate.
    Type: Application
    Filed: August 31, 2016
    Publication date: July 12, 2018
    Applicant: AISIN AW CO., LTD.
    Inventor: Takanobu NARUSE