Patents by Inventor Takanobu Naruse
Takanobu Naruse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180052784Abstract: A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first memory interface, a second memory controller configured to output a second control signal to the second external memory through a second memory interface, an inter-device interface for communicating with another semiconductor device, terminals configured to output the second control signal that has passed through the second memory interface, and a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode of the semiconductor device and to couple the selected interface to the terminals.Type: ApplicationFiled: October 27, 2017Publication date: February 22, 2018Inventors: Kenichiro OMURA, Ryohei YOSHIDA, Takanobu NARUSE, Seiichi SAITO
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Publication number: 20180024747Abstract: A memory controller that suppresses noise generated when data is transferred to a memory, includes a write part portion that writes transmission data into the memory, and a read portion that reads data from the memory. The write portion includes a substitution unit that substitutes, when a linear sequence of a bit of “1” and a bit of “0” of a bit string configuring data transmitted through the signal line is a target pattern set as a substitution target, a substitutional bit string that suppresses noise for the bit string, before the transmission data is written into the memory. The read portion includes a restoration unit that restores a substitutional bit string read from the memory to an initial bit string.Type: ApplicationFiled: March 24, 2016Publication date: January 25, 2018Applicant: AISIN AW CO., LTD.Inventor: Takanobu NARUSE
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Patent number: 9830281Abstract: A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first memory interface, a second memory controller configured to output a second control signal to the second external memory through a second memory interface, an inter-device interface for communicating with another semiconductor device, terminals configured to output the second control signal that has passed through the second memory interface, and a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode of the semiconductor device and to couple the selected interface to the terminals.Type: GrantFiled: November 19, 2013Date of Patent: November 28, 2017Assignee: Renesas Electronics CorporationInventors: Kenichiro Omura, Ryohei Yoshida, Takanobu Naruse, Seiichi Saito
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Patent number: 9647654Abstract: A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result.Type: GrantFiled: September 11, 2015Date of Patent: May 9, 2017Assignee: Renesas Electronics CorporationInventors: Tadashi Kameyama, Takanobu Naruse, Yohei Akita, Hirotaka Hara
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Publication number: 20160282202Abstract: To suppress an increase in the number of voltage comparators with an expansion in a chip temperature detection range, a temperature sensor in a semiconductor device includes a temperature detection circuit for outputting a voltage according to the chip temperature, a reference voltage generating circuit for generating a plurality of reference voltages, and a plurality of voltage comparators for comparing each reference voltage obtained by the reference voltage generating circuit with an output voltage of the temperature detection circuit and thereby generating a chip temperature detection signal configured with multiple bits. Further, the temperature sensor includes a control circuit for controlling the reference voltages generated by the reference voltage generating circuit based on the chip temperature detection signal and thereby changing correspondence between the chip temperature detection signal and the chip temperature to shift a chip temperature detection range.Type: ApplicationFiled: June 9, 2016Publication date: September 29, 2016Inventors: Tadashi KAMEYAMA, Takanobu NARUSE, Takayasu ITO
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Patent number: 9389127Abstract: A temperature sensor in a semiconductor device includes a temperature detection circuit for outputting a voltage according to the chip temperature, a reference voltage generating circuit for generating a plurality of reference voltages, and a plurality of voltage comparators for comparing each reference voltage with an output voltage of the temperature detection circuit and thereby generating a chip temperature detection signal configured with multiple bits. Further, the temperature sensor includes a control circuit for controlling the reference voltages generated by the reference voltage generating circuit based on the chip temperature detection signal and thereby changing correspondence between the chip temperature detection signal and the chip temperature to shift a chip temperature detection range.Type: GrantFiled: September 12, 2012Date of Patent: July 12, 2016Assignee: Renesas Electronics CorporationInventors: Tadashi Kameyama, Takanobu Naruse, Takayasu Ito
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Publication number: 20160006424Abstract: A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result.Type: ApplicationFiled: September 11, 2015Publication date: January 7, 2016Inventors: Tadashi Kameyama, Takanobu Naruse, Yohei Akita, Hirotaka Hara
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Publication number: 20150311904Abstract: A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.Type: ApplicationFiled: June 10, 2015Publication date: October 29, 2015Inventors: Hajime Sasaki, Hirohiko Ito, Shikiko Nachi, Takanobu Naruse
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Patent number: 9146598Abstract: A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result.Type: GrantFiled: January 28, 2014Date of Patent: September 29, 2015Assignee: Renesas Electronics CorporationInventors: Tadashi Kameyama, Takanobu Naruse, Yohei Akita, Hirotaka Hara
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Patent number: 9083353Abstract: A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.Type: GrantFiled: July 27, 2013Date of Patent: July 14, 2015Assignee: Renesas Electronics CorporationInventors: Hajime Sasaki, Hirohiko Ito, Shikiko Nachi, Takanobu Naruse
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Publication number: 20140210544Abstract: A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result.Type: ApplicationFiled: January 28, 2014Publication date: July 31, 2014Applicant: Renesas Mobile CorporationInventors: TADASHI KAMEYAMA, TAKANOBU NARUSE, YOHEI AKITA, HIROTAKA HARA
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Publication number: 20140189259Abstract: A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first memory interface, a second memory controller configured to output a second control signal to the second external memory through a second memory interface, an inter-device interface for communicating with another semiconductor device, terminals configured to output the second control signal that has passed through the second memory interface, and a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode of the semiconductor device and to couple the selected interface to the terminals.Type: ApplicationFiled: November 19, 2013Publication date: July 3, 2014Applicant: Renesas Mobile CorporationInventors: Kenichiro Omura, Ryohei Yoshida, Takanobu Naruse, Seiichi Saito
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Patent number: 8659927Abstract: In a wiring substrate, a double data rate (DDR) memory and a memory controller controlling the DDR memory are mounted. Further, in the wiring substrate, plural equal-length wires connecting the DDR memory and the memory controller are formed. The plural equal-length wires include a differential transmission line, such as a clock wire transmitting a clock signal, which is connected via a common mode choke coil. The differential transmission line may have a wire length shorter than a wire length of another equal-length wire, by a wire length corresponding to delay time of a transmission signal due to the common mode choke coil.Type: GrantFiled: June 8, 2011Date of Patent: February 25, 2014Assignees: Murata Manufacturing Co., Ltd, Renesas Electronics CorporationInventors: Takashi Ichimura, Takanobu Naruse, Chiaki Fujii
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Publication number: 20140043075Abstract: A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.Type: ApplicationFiled: July 27, 2013Publication date: February 13, 2014Applicant: Renesas Mobile CorporationInventors: Hajime Sasaki, Hirohiko Ito, Shikiko Nachi, Takanobu Naruse
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Publication number: 20130073240Abstract: A temperature sensor in a semiconductor device includes a temperature detection circuit for outputting a voltage according to the chip temperature, a reference voltage generating circuit for generating a plurality of reference voltages, and a plurality of voltage comparators for comparing each reference voltage with an output voltage of the temperature detection circuit and thereby generating a chip temperature detection signal configured with multiple bits. Further, the temperature sensor includes a control circuit for controlling the reference voltages generated by the reference voltage generating circuit based on the chip temperature detection signal and thereby changing correspondence between the chip temperature detection signal and the chip temperature to shift a chip temperature detection range.Type: ApplicationFiled: September 12, 2012Publication date: March 21, 2013Inventors: Tadashi KAMEYAMA, Takanobu Naruse, Takayasu Ito
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Publication number: 20110305060Abstract: In a wiring substrate, a double data rate (DDR) memory and a memory controller controlling the DDR memory are mounted. Further, in the wiring substrate, plural equal-length wires connecting the DDR memory and the memory controller are formed. The plural equal-length wires include a differential transmission line, such as a clock wire transmitting a clock signal, which is connected via a common mode choke coil. The differential transmission line may have a wire length shorter than a wire length of another equal-length wire, by a wire length corresponding to delay time of a transmission signal due to the common mode choke coil.Type: ApplicationFiled: June 8, 2011Publication date: December 15, 2011Applicants: RENESAS ELECTRONICS CORPORATION, MURATA MANUFACTURING CO., LTD.Inventors: Takashi ICHIMURA, Takanobu NARUSE, Chiaki FUJII
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Patent number: 8032715Abstract: The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory.Type: GrantFiled: August 2, 2010Date of Patent: October 4, 2011Assignee: Renesas Electronics CorporationInventors: Fumie Katsuki, Takanobu Naruse, Chiaki Fujii
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Publication number: 20100318732Abstract: The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory.Type: ApplicationFiled: August 2, 2010Publication date: December 16, 2010Inventors: Fumie Katsuki, Takanobu Naruse, Chiaki Fujii
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Patent number: 7783827Abstract: The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory.Type: GrantFiled: March 24, 2009Date of Patent: August 24, 2010Assignee: Renesas Technology Corp.Inventors: Fumie Katsuki, Takanobu Naruse, Chiaki Fujii
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Publication number: 20090182943Abstract: The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory.Type: ApplicationFiled: March 24, 2009Publication date: July 16, 2009Inventors: FUMIE KATSUKI, Takanobu NARUSE, Chiaki FUJII