Abstract: A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage.

Abstract: The present disclosure adjusts the voltage threshold values of select gates of NAND strings. The select gates of the NAND string can be read, erased, and programmed.

Abstract: A device and corresponding method of using a temperature dependent bias generator to generate a voltage that is applied to a control gate of a sense amplifier is disclosed. By applying the temperature dependent bias signal to the sense amplifier, a substantially temperature independent disclosing time can be achieved at a sense node of a sense amplifier.

Abstract: The present disclosure adjusts the voltage threshold values of select gates of NAND strings. The select gates of the NAND string can be read, erased, and programmed.

Abstract: A sense amplifier includes a reference voltage generator for generating a reference output voltage and a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage or includes a plurality of amplifier transistors each conducting a portion of a core current through a current conducting device such as core cell. The sizes and/or connections of transistors of such components result in high voltage swing and thus high sensitivity of the sense amplifier.

Abstract: A self sensing reference system and method are described. The self sensing reference systems and methods facilitate efficient accurate access to information. In one embodiment, a self sensing reference system includes a main cascode component, a self referencing component, and a comparison verification component. The main cascode component receives input on a first current value and a second current value. The self referencing component establishes a plurality of data indications wherein a first data indication is established based upon a comparison of the first current value to the second current value. A comparison verification component verifies a second data indication.

Abstract: A sense amplifier includes a reference voltage generator for generating a reference output voltage and a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage or includes a plurality of amplifier transistors each conducting a portion of a core current through a current conducting device such as core cell. The sizes and/or connections of transistors of such components result in high voltage swing and thus high sensitivity of the sense amplifier.

Abstract: A sense amplifier includes a reference voltage generator for generating a reference output voltage and a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage or includes a plurality of amplifier transistors each conducting a portion of a core current through a current conducting device such as core cell. The sizes and/or connections of transistors of such components result in high voltage swing and thus high sensitivity of the sense amplifier.

Abstract: Non-volatile memory, such as Flash memory, is programmed by writing a window of information to memory. The programmed/non-programmed state of each memory cell may be dynamically determined for each window and stored as an indication bit. These techniques can provide for improved average power drain and a reduced maximum current per window during programming.

Abstract: The present invention provides a method for determining program and erase states in flash memory devices. Specifically, one embodiment of the present invention discloses a method for minimizing false detection of states in an array of non-volatile floating gate memory cells. A plurality of word lines are arranged in a plurality of rows. A plurality of bit lines are arranged in a plurality of columns. The method begins by determining a selected bit line that is associated with a column of memory cells. Then, the method continues by biasing a group of word lines at a negative voltage. The group of word lines are electrically coupled to the associated memory cells. The application of negative voltage to the group of word lines limits leakage current contributions from the associated memory cells in the column of memory cells when performing a verify operation.

Abstract: According to one exemplary embodiment, a memory array includes a number of bitlines. The memory array further includes a voltage supply circuit, where the voltage supply circuit is configured to receive an operating voltage and a control signal and to output a low output voltage in a switching mode and a high output voltage in a programming mode. The low output voltage can be approximately equal to the operating voltage in the switching mode. In the programming mode, the high output voltage is greater than the operating voltage. According to this exemplary embodiment, the voltage supply circuit is in the programming mode when one of the bitlines is selected for programming. The voltage supply circuit is in the switching mode if none of the bitlines is selected for programming. The high output voltage can cause a bitline programming voltage to be applied to a selected bitline in the programming mode.

Abstract: A memory array includes a plurality of memory banks, each having a plurality of sectors and a plurality of sector decoders, each sector decoder operatively associated with a sector. A first plurality of lines provides first signals, and a second plurality of lines provides second signals. A first decoder apparatus is operatively associated with the first plurality of lines for receiving the first signals and for providing a first address signal by means of a first single line to a sector decoder of a memory bank. A second decoder apparatus is operatively associated with the second plurality of lines for receiving the second signals and for providing a second address signal by means of a second single line to a sector decoder of a memory bank.

Abstract: According to one exemplary embodiment, a semiconductor die includes a memory core array situated over a substrate, where the memory core array includes a number of bitlines, where the bitlines can be situated in a first interconnect metal layer in the semiconductor die. The semiconductor die further includes an interconnect structure situated over the memory core array, where the interconnect structure is situated in a second interconnect metal layer in the semiconductor die and situated over each of the bitlines. The interconnect structure can include at least one interconnect line, which can form an angle with respect to the bitlines that can be greater than 0.0 degrees and less than or equal to 90.0 degrees. The interconnect structure can form one of a number of capacitances with each of the bitlines, where each of the capacitances can be substantially equal in value to each other of the capacitances.

Abstract: A semiconductor device includes a first cascode circuit having a first current mirror amplifying a reference current flowing through a data line of a reference cell, and a second current mirror generating a first potential from an amplified reference current; and a second cascode circuit having a third current mirror amplifying a core current flowing through a data line of a core cell, and a transistor receiving a gate voltage corresponding to the amplified reference current and generating a second potential based on a difference between an amplified core cell current and the amplified reference current. Since the second potential is generated by the difference between the core cell current and the reference cell current, the second potential swings in the full range of the ground power supply voltage to the ground potential, and the range of the amplitude of the power supply voltage can be efficiently utilized. Sensing is enabled for a fine current margin.

Abstract: Non-volatile memory, such as Flash memory, is programmed by writing a window of information to memory. The programmed/non-programmed state of each memory cell may be dynamically determined for each window and stored as an indication bit. These techniques can provide for improved average power drain and a reduced maximum current per window during programming.

Abstract: According to one exemplary embodiment, a semiconductor die includes a memory core array situated over a substrate, where the memory core array includes a number of bitlines, where the bitlines can be situated in a first interconnect metal layer in the semiconductor die. The semiconductor die further includes an interconnect structure situated over the memory core array, where the interconnect structure is situated in a second interconnect metal layer in the semiconductor die and situated over each of the bitlines. The interconnect structure can include at least one interconnect line, which can form an angle with respect to the bitlines that can be greater than 0.0 degrees and less than or equal to 90.0 degrees. The interconnect structure can form one of a number of capacitances with each of the bitlines, where each of the capacitances can be substantially equal in value to each other of the capacitances.

Abstract: A decoder for a memory device includes driving devices each applying a respective line voltage to a respective line of the memory device when turned on. The decoder also includes a control device coupled to the plurality of driving devices at a common node for generating a voltage that controls the driving devices to turn on or off. Also, a capacitor coupled to the common node increases the voltage at the common node from an initial boost voltage to a final boost voltage. Thus, a line of a memory device is driven to a boost voltage with minimized area and wiring complexity.

Abstract: A decoder for a memory device includes driving devices each applying a respective line voltage to a respective line of the memory device when turned on. The decoder also includes a control device coupled to the plurality of driving devices at a common node for generating a voltage that controls the driving devices to turn on or off. Also, a capacitor coupled to the common node increases the voltage at the common node from an initial boost voltage to a final boost voltage. Thus, a line of a memory device is driven to a boost voltage with minimized area and wiring complexity.

Abstract: A sense amplifier includes a reference voltage generator for generating a reference output voltage and a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage or includes a plurality of amplifier transistors each conducting a portion of a core current through a current conducting device such as core cell. The sizes and/or connections of transistors of such components result in high voltage swing and thus high sensitivity of the sense amplifier.

Abstract: A semiconductor device includes a first cascode circuit having a first current mirror amplifying a reference current flowing through a data line of a reference cell, and a second current mirror generating a first potential from an amplified reference current; and a second cascode circuit having a third current mirror amplifying a core current flowing through a data line of a core cell, and a transistor receiving a gate voltage corresponding to the amplified reference current and generating a second potential based on a difference between an amplified core cell current and the amplified reference current. Since the second potential is generated by the difference between the core cell current and the reference cell current, the second potential swings in the full range of the ground power supply voltage to the ground potential, and the range of the amplitude of the power supply voltage can be efficiently utilized. Sensing is enabled for a fine current margin.