Abstract: A protection system that protects a booster circuit used to boost operating signals in a memory device. The system includes a protection circuit for protecting an output transistor of the booster circuit. The protection circuit includes a transfer gate coupled to the output transistor and coupled to receive a first boost signal and a second boost signal. The transfer gate opens and closes in response to the second boost signal. When the transfer gate is closed, the first boost signal is uncoupled from the output transistor, and when the transfer gate is opened, the first boost signal is coupled to the output transistor. The circuit also includes a protection transistor coupled to the second boost signal, a supply voltage and the output transistor, where the protection transistor couples the supply voltage to the output transistor when the transfer gate is closed.

Abstract: A word line driver for flash memories using NMOS circuitry to reduce parasitic capacitance loading on boost circuitry in low-voltage applications. A delay scheme which delays turn-on of the driver's source-drain circuit for a short time after the turn-on of the driver transistors' gates allows the gate capacitance of the driver transistor to provide an extra boost.

Abstract: Reading data from a core memory consumes more power when the data sets being driven change state, especially when bursting out the data at high speed. Power saving for a burst mode implementation improves the power consumed by inverting the data sets whenever a majority of the data changes states from set to set and including a separate output indicating whether the data being driven is inverted. Present data is selected from the core memory and clocked into the power saving arrangement. The present data is compared with previously selected data to determine whether the majority of data presently selected has changed from the previously selected data. In addition, the present selected data is also delayed and then subjected to a logical XOR function with the majority determination above. Finally, the data subjected to the logical XOR function and the majority determination are driven separately to external elements requesting the present data.

Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

Abstract: A system and a method are disclosed for providing a power saving mode during reading a memory device. A new memory content is read from the memory and, before being put at the memory output bus, is compared with the previously read memory content, which is currently on the output bus of the memory device. If the result of the comparison indicates that more than half of the memory output bits have to be toggled in order to put the new memory content on the memory output bus, the new data is inverted internally in order to reduce the number of output pins toggles. Then, the memory device sends a signal to the microprocessor or microcontroller indicating that the new data is inverted, and that the new data has to be inverted back before being put on the memory output bus.

Abstract: A system and a method are disclosed for providing a power saving mode during reading a memory device. A new memory content is read from the memory and, before being put at the memory output bus, is compared with the previously read memory content, which is currently on the output bus of the memory device. If the result of the comparison indicates that more than half of the memory output bits have to be toggled in order to put the new memory content on the memory output bus, the new data is inverted internally in order to reduce the number of output pins toggles. Then, the memory device sends a signal to the microprocessor or microcontroller indicating that the new data is inverted, and that the new data has to be inverted back before being put on the memory output bus.

Abstract: The present invention discloses a wordline voltage regulation method and system that provides a predetermined voltage as a wordline voltage to a plurality of wordlines during read mode. A supply voltage (Vcc) is regulated and temperature compensated by a wordline driver circuit to provide the predetermined voltage that is lower in magnitude than the magnitude of the supply voltage (Vcc). The wordline driver circuit is activated by an activation circuit when the read operation is initiated. During the read operation, the wordline driver circuit maintains the predetermined voltage during variations in the supply voltage (Vcc) as well as variations in a process load supplied by the wordline driver circuit.

Abstract: A pre-amplifier portion of a sense amplifier for a dual bank architecture simultaneous operation flash memory device is provided. The sense pre-amplifier circuit includes two inverting amplifiers, the second inverting amplifier providing a feedback loop for the first inverting amplifier. In addition, special “kicker” circuitry raises the sense pre-amplifier's input signal line to its operating level. The combination of inverting amplifiers, feedback loop and level raising circuitry is configured to provide higher bandwidths for the sense pre-amplifier to accommodate low capacitive loading resulting from a small memory bank. The combination is also configured to provide faster raising of the input signal line to operating level to accommodate high capacitive loading resulting from a large memory bank. The combination is also configured to provide increased signal margins at the output of the sense pre-amplifier.

Abstract: A sense amplifier output equalization circuit for a variable operating voltage high density flash memory device is disclosed. The equalization circuit compensates for the varying sensing speeds due to the varying operating voltages by variably adjusting the duration of an equalization pulse which is used to equalize the output stage of the sense amplifier to the input stage.

Abstract: A voltage boost circuit (111) for a flash memory (100) includes a boosting circuit (110), which is capable of boosting a portion of a power supply voltage (VCC) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array (102) of the memory. The voltage boost circuit further includes a balancing or clamping circuit (112) for providing a nonzero adjustment voltage (VCL) to the boosting circuit to reduce the portion of the supply voltage that is available for boosting by the boosting circuit when the power supply voltage exceeds a certain value.

Abstract: A flash memory having word line decoding and selection architecture is described. The flash memory include first and second sectors of memory cells, first and second local driver circuits, first, second and third decoding circuits, and a driving circuit. The first sectors of first memory cells include a first plurality of word lines coupled to the first memory cells, each being capable of being a first selected word line. The second sectors of second memory cells include a similar Local driver circuits are independently coupled to each word line of the first and second pluralities of word lines of the first sectors. Each decoding circuits comprise a first and a second side of decoding circuitry. The first side of decoding circuitry activates a first selected plurality of local driver circuits and the second side of decoding circuitry activates a second selected plurality of local driver circuits.

Abstract: A burst mode architecture to provide burst mode access to a plurality of data words in a flash memory is described. The burst mode architecture includes a first circuit, a control circuit coupled to the first circuit, and a data buffer selectively coupled to the first circuit by the control circuit. The first circuit accesses a plurality of data words, beginning with an initial access of a first data word and a second data word. The control circuit generates a timing signal having pulses and a second signal. The second signal is generated upon completion of the initial access of the first data word and the second data word. The first circuit follows the initial access with subsequent accesses of the plurality of data words responsively to the second signal and the timing signal.

Abstract: Reading data from a core memory consumes more power when the data sets being driven change state, especially when bursting out the data at high speed. Power saving for a burst mode implementation improves the power consumed by inverting the data sets whenever a majority of the data changes states from set to set and including a separate output indicating whether the data being driven is inverted. Present data is selected from the core memory and clocked into the power saving arrangement. The present data is compared with previously selected data to determine whether the majority of data presently selected has changed from the previously selected data. In addition, the present selected data is also delayed and then subjected to a logical XOR function with the majority determination above. Finally, the data subjected to the logical XOR function and the majority determination are driven separately to external elements requesting the present data.

Abstract: A dual bank flash memory device including a reference path equalization circuits is disclosed. In the device, each bank includes a read path with an electrical characteristic. The device further includes a reference circuit which comprises a reference cell and reference paths which also have an electrical characteristic. The reference equalization circuits are coupled with the reference circuit which equalizes the read path electrical characteristics with the reference path electrical characteristics.

Abstract: A device for performing redundant reading in a flash memory is provided. The device includes arrays of regular memory cells and arrays of redundant memory cells. Some of the regular memory cells may be defective and those will have defective addresses. A regular sense amplifier will read the regular memory cells at their accessed address while at a time no later a redundant sense amplifier will read the redundant memory cells. A first array of CAM's will store the defective addresses of the defective memory cells while a second array of CAM's will store the input/output designators of the defective memory cells. Address matching circuitry will compare the accessed addresses with the defective addresses to determine whether the accessed address is defective. Before the end of the reading intervals of the sense amplifiers, decoding circuitry will decode the input/output designators of both the defective and non-defective memory cells.

Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

Abstract: A flash memory device is provided with a two stage sense amplifier. The two stage sense amplifier includes a sense pre-amplifier coupled to a sense output amplifier. The sense pre-amplifier amplifies a data signal from a memory bank. The sense output amplifier then differentially compares the output of the sense pre-amplifier with a reference signal. An embodiment with first and second memory banks is also provided that is capable of simultaneous operation.

Abstract: A decoder circuit has two separate portions, a low voltage portion and a high voltage portion. Through the use of the high voltage portion, the decoder circuit is capable of supplying high program voltage. Through the use of low voltage portion and isolated from the high voltage portion, quick read operation is performed.

Abstract: A voltage boost circuit (111) for a memory (100) includes a boosting circuit (110) which is coupled to a boosted node (120) to boost a word line voltage for accessing a core cell of the memory. The voltage boost circuit further includes a reset circuit (112) coupled to the boosted node and including a switchable zero-threshold transistor (202) for resetting the boosted node to a reset voltage (VCC).