Abstract: When a void is caused in an interlayer insulating film on a semiconductor substrate, the invention prevents short circuit between two or more contact plugs that sandwich the void therebetween via a conductive film buried in the void at the time of formation of the contact plugs. An element isolation region having an upper surface lower than a main surface of the semiconductor substrate is formed inside a trench in the main surface of the semiconductor substrate, so that a void formed immediately above the semiconductor substrate in an active region and a void formed immediately above the element isolation region are divided from each other. In this manner, a conductive film is prevented from being buried in the second void.

Abstract: To provide a semiconductor device capable of preventing short circuit between first and second gate electrodes. The semiconductor device has a semiconductor substrate, gate insulating film, first gate electrode, stacked film, and second gate electrode. The semiconductor substrate has a first surface including a first region and a second region adjacent thereto. The gate insulating film is placed on the semiconductor substrate in the first region. The first gate electrode is placed on the gate insulating film and has a side surface. The stacked film has a first oxide film on the second region and on the side surface of the first gate electrode, a nitride film on the first oxide film, and a second oxide film on the nitride film. The second gate electrode is placed on the stacked film in the second region. The side surface above the second gate electrode includes a protrusion toward the side of the second gate electrode.

Abstract: When a void is caused in an interlayer insulating film on a semiconductor substrate, the invention prevents short circuit between two or more contact plugs that sandwich the void therebetween via a conductive film buried in the void at the time of formation of the contact plugs. An element isolation region having an upper surface lower than a main surface of the semiconductor substrate is formed inside a trench in the main surface of the semiconductor substrate, so that a void formed immediately above the semiconductor substrate in an active region and a void formed immediately above the element isolation region are divided from each other. In this manner, a conductive film is prevented from being buried in the second void.

Abstract: The production of a crack in an insulating film under an external terminal of a semiconductor device due to external force applied to the external terminal is suppressed or prevented. Over the principal surface of a semiconductor substrate, there are formed multiple wiring layers. In the fifth wiring layer directly under the uppermost wiring layer of the wiring layers, the following measure is taken: a conductor pattern (fifth wiring, dummy wiring, and plug) is not formed directly under the probe contact area of each bonding pad PD in the uppermost wiring layer. In the fifth wiring layer, conductor patterns (fifth wiring, dummy wirings, and plugs) are formed in the areas other than directly under the probe contact area of each bonding pad in the uppermost wiring layer.

Abstract: The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed. Over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11, insulating films 14, 15, 16 are formed. An opening is formed in those insulating films and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 to form the opening. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance. By interposing the insulating film 14 therebetween with a higher density of Si (silicon) atoms than the insulating film 11, an electrically weak interface is prevented from being formed.

Abstract: The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.

Abstract: The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.

Abstract: To suppress or prevent the generation of a crack in an insulating film below an external terminal which could be caused by an external force added to the external terminal of a semiconductor device. A top wiring layer MH of wiring layers formed on a main surface of a silicon substrate has a pad comprising a conductor pattern containing aluminum. On an undersurface of the pad, there are arranged a barrier conductor film formed by laminating, from below, a first barrier conductor film and a second barrier conductor film. Of a fifth wiring layer which is one layer lower than the top wiring layer, in an area overlapping with a probe contact area of the pad in a plane, the conductor pattern is not arranged. Further, the first and second barrier conductor films are the conductor films including titanium and titanium nitride as principal components, respectively. Also, the first barrier conductor film is thicker than the second barrier conductor film.

Abstract: The production of a crack in an insulating film under an external terminal of a semiconductor device due to external force applied to the external terminal is suppressed or prevented. Over the principal surface of a semiconductor substrate, there are formed multiple wiring layers. In the fifth wiring layer directly under the uppermost wiring layer of the wiring layers, the following measure is taken: a conductor pattern (fifth wiring, dummy wiring, and plug) is not formed directly under the probe contact area of each bonding pad PD in the uppermost wiring layer. In the fifth wiring layer, conductor patterns (fifth wiring, dummy wirings, and plugs) are formed in the areas other than directly under the probe contact area of each bonding pad in the uppermost wiring layer.

Abstract: The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.

Abstract: An interconnection structure includes a lower interconnection layer formed on a substrate and composed of a copper layer, an interlayer insulating layer formed on the lower interconnection layer and having a via reaching the lower interconnection layer, an upper interconnection layer electrically connected to the lower interconnection layer through the via, and composed of a copper layer formed in the interlayer insulating layer, and a barrier metal layer formed between the upper interconnection layer and the interlayer insulating layer. The barrier metal layer has an opening in a bottom portion of the via, and through that opening, the upper interconnection layer comes in direct contact with the lower interconnection layer in the bottom portion of the via. Thus, an interconnection structure suppressing concentration of voids in an interconnection under a via due to stress migration can be attained.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a copper layer by plating, forming a defect trapping film on the copper layer, moving a defect in the copper layer into the defect trapping film by annealing or the like, and removing the defect trapping film. Thereby, a semiconductor device in which concentration of micro-voids in a portion in proximity to a bottom of a via due to stress migration can be restrained and a method of manufacturing the same can be obtained.

Abstract: An interconnection structure includes a lower interconnection layer formed on a substrate and composed of a copper layer, an interlayer insulating layer formed on the lower interconnection layer and having a via reaching the lower interconnection layer, an upper interconnection layer electrically connected to the lower interconnection layer through the via, and composed of a copper layer formed in the interlayer insulating layer, and a barrier metal layer formed between the upper interconnection layer and the interlayer insulating layer. The barrier metal layer has an opening in a bottom portion of the via, and through that opening, the upper interconnection layer comes in direct contact with the lower interconnection layer in the bottom portion of the via. Thus, an interconnection structure suppressing concentration of voids in an interconnection under a via due to stress migration can be attained.

Abstract: A semiconductor device has a substrate 1, a metal wiring 3 formed on the substrate 1 and covered with the films of a high-melting-point metal 2 and 4 immediately above and below and an interlayer insulating film 5 formed by a plasma CVD method so as to cover the metal wiring 3.

Abstract: A method for manufacturing a semiconductor device wherein a contact hole formed in an interlayer insulating film on a semiconductor substrate is filled with a plug for electrically connecting an overlying conductor layer with an underlying conductor layer. The plug fills the contact hole, and comprised a tungsten film the upper end whereof is positioned below the upper surface of the interlayer insulating film, and a tungsten film which is filled on the tungsten film in the contact hole and the upper surface whereof is on substantially the same level as the upper surface of the interlayer insulating film.

Abstract: The upper surface of a second interlayer insulating film (3) and the upper surface of a first interconnect line (11) made of copper are different in height. Therefore, in the upper surface of a three-layered film provided thereon for constituting an MIM capacitor (13), difference in level is generated at the position corresponding to that of the first interconnect line (11). During patterning of this three-layered film, it is possible to optically detect the position of the difference, whereby the position of the first interconnect line (11) can be detected. As a result, alignment between the MIM capacitor (13) and the first interconnect line (11) can be precisely performed.

Abstract: The present invention protects a wiring against an etchant when a fuse connected to this wiring is subjected to a laser blow. A fuse has a barrier metal at its lower side. A plug is connected to the lower side of the fuse. The plug has a barrier metal at least at its lower side. Even if the fuse is partly removed through the laser blow at a region other than a portion where the fuse is connected to the plug, two layers of the barrier metals remain between the removed portion and a lower wiring. This enlarges the margin for preventing the adverse influence, such as corrosion and breaking of the lower wiring, brought by an etchant associated in other manufacturing process.

Abstract: The invention provides a method of manufacturing a semiconductor device which can reduce or prevent abrasive material from remaining in an indentation in a surface after a CMP process. After forming a titanium nitride film (5), a tungsten film (6) is formed on an entire surface. The temperature is set at approximately 430° C. for the reaction and, first, 50 sccm of WF6, 10 sccm of SiH4 and 1000 sccm of H2 are used in the atmosphere of 30 Torr of Ar, N2 so as to form a seed layer with a film thickness of approximately 100 nm. After that, in the atmosphere of 80 Torr of Ar, N2, 75 sccm of WF6 and 500 sccm of H2 are used as a reactive gas so as to layer a film with a thickness of approximately 300 nm. The tungsten film (6) has grains (6a) in a pillar form of which the grain diameter is small to the degree that the abrasive material (50) used in the CMP process does not easily become caught in the gaps between the grains.

Abstract: A method for manufacturing a semiconductor device wherein a contact hole formed in an interlayer insulating film on a semiconductor substrate is filled with a plug for electrically connecting an overlying conductor layer with an underlying conductor layer. The plug fills the contact hole, and comprised a tungsten film the upper end whereof is positioned below the upper surface of the interlayer insulating film, and a tungsten film which is filled on the tungsten film in the contact hole and the upper surface whereof is on substantially the same level as the upper surface of the interlayer insulating film.

Abstract: A method and apparatus for manufacturing a semiconductor device having an interlayer insulating film of improved flatness after a CMP process are obtained. The method includes the steps of: heat-treating a semiconductor device having an interlayer insulating film containing impurities; conducting a process for making an impurity-concentration distribution at an upper layer portion of the interlayer insulating film substantially uniform after the heat treatment; and polishing the interlayer insulating film by a CMP process after the process for making the impurity-concentration distribution substantially uniform.