Patents by Inventor Takao Kamoshima

Takao Kamoshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020177325
    Abstract: The invention provides a method of manufacturing a semiconductor device which can reduce or prevent abrasive material from remaining in an indentation in a surface after a CMP process.
    Type: Application
    Filed: November 7, 2001
    Publication date: November 28, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hiroki Takewaka, Takao Kamoshima, Junko Izumitani
  • Publication number: 20020093097
    Abstract: There is provided a W plug formation method which prevents occurrence of a clearance or void around a W plug after HF cleansing as well as occurrence of an increase in resistance of a via hole and that of a contact hole, and occurrence of open failures. A surface layer section of a Ti film-which has been formed as barrier metal film in a hole formed in an interlayer dielectric film on a lower interconnection-is oxidized by means of oxygen plasma processing, thereby forming a Ti oxide film. Thus, the surface of the Ti film is not exposed on the surface. There can be prevented elution of the Ti film, which would otherwise be caused by HF cleansing effected in a subsequent process, and occurrence of a clearance or void, which would otherwise arise around a conductive plug.
    Type: Application
    Filed: July 24, 2001
    Publication date: July 18, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Takao Kamoshima, Takashi Yamashita, Yoshifumi Takata
  • Publication number: 20020081836
    Abstract: There are provided a cell plate layer 5 formed in the insulating films 10 and 11 on a semiconductor substrate 4. A connecting hole 12 is formed through the insulating films 10 and 11 and the cell plate layer 5, and the circumference of the side surface of the cell plate layer is exposed. A conducting plug 7A is formed by filling the connecting hole 12 with a conductor so as to contact the circumference of the side surface, for example, an upper surface of the cell plate layer 5. By increasing a contact area between a conductor layer and a conducting member, a contact resistance is lowered, and a stable and reliable semiconductor device is obtained.
    Type: Application
    Filed: May 17, 2001
    Publication date: June 27, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hiroki Takewaka, Takao Kamoshima, Junko Izumitani
  • Publication number: 20020019134
    Abstract: A method and apparatus for manufacturing a semiconductor device having an interlayer insulating film of improved flatness after a CMP process are obtained. The method includes the steps of: heat-treating a semiconductor device having an interlayer insulating film containing impurities; conducting a process for making an impurity-concentration distribution at an upper layer portion of the interlayer insulating film substantially uniform after the heat treatment; and polishing the interlayer insulating film by a CMP process after the process for making the impurity-concentration distribution substantially uniform.
    Type: Application
    Filed: February 14, 2001
    Publication date: February 14, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takeru Matsuoka, Takashi Yamashita, Takao Kamoshima
  • Publication number: 20010017415
    Abstract: A semiconductor device with high reliability is provided in which an insulating property of an insulating layer is high and connection failure is prevented.
    Type: Application
    Filed: February 9, 2001
    Publication date: August 30, 2001
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takao Kamoshima, Hiroki Takewaka, Takashi Yamashita
  • Patent number: 6214723
    Abstract: A method of manufacturing a semiconductor device with high reliability is provided in which an insulating property of an insulating layer is high and connection failure is prevented. The semiconductor device includes: a silicon substrate; a low-temperature aluminum film formed on silicon substrate and including a polycrystal; and a high-temperature aluminum film. An opening is formed in a surface of a high-temperature aluminum film by a crystal grain boundary. A distance between side walls of the opening becomes small as closer to silicon substrate.
    Type: Grant
    Filed: September 8, 1999
    Date of Patent: April 10, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takao Kamoshima, Hiroki Takewaka, Takashi Yamashita