Abstract: An inrush current at beginning of operation of a charge pump circuit is reduced to prevent adverse effect on other circuits in a system. Charge transfer MOS transistors are connected in series. One end of each coupling capacitor is connected to each connecting point of the charge transfer MOS transistors. An output from each clock driver is applied on the other end of the respective coupling capacitor. Each clock driver includes a first clock driver and a second clock driver having higher driving capacity than the first clock driver. Each clock driver is controlled so that the first clock driver is put into operation at first and at the end of a predetermined elapsed time it is stopped and the second clock driver is put into operation.

Abstract: An abnormal reduction in a positive high power supply electric potential VH outputted by a positive booster charge pump circuit at switching of an output stage inverter in a driver circuit is prevented. An output of an inverter INV2 is applied to an input terminal of an inverter INV4 for controlling an output transistor, and an output of the inverter INV4 is applied to a gate of an N-channel type MOS transistor of the output stage inverter INV6. The inverter INV4 is made of a P-channel type MOS transistor, a first resistor and an N-channel type MOS transistor connected between a positive high power supply electric potential VH and a negative high power supply electric potential VL, making a connecting node between the first resistor and the N-channel type MOS transistor an output terminal of the inverter INV4.

Abstract: Charge transfer MOS transistors M1 and M2 at front two stages are constructed of an N-channel type, and charge transfer MOS transistors at rear two stages are constructed of an P-channel type. Inverting level shift circuits S1 and S2 and non-inverting level shift circuits S3 and S4, which can produces an intermediate potential are provided. Because of such a configuration, a charge pump circuit which can realize high efficiency and provide a large output current can be realized. In addition, the gate/source voltage Vgs (transistors are in the ON state) of the charge transfer MOS transistors can be uniformed to 2Vdd.

Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer. P+-type buried layers abutting on bottoms of the P-type well regions and N+-type buried layers abutting on bottoms of the P+-type buried layers and electrically isolating the P-type well regions from the single crystalline silicon substrate are formed. An MOS transistor is formed in each of the P-type well regions and a drain layer of the MOS transistor and each of the P-type well regions are electrically connected.

Abstract: In a charge pump device, occurrence of a latch up can be prevented and current capacity can be increased. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, P-type well regions are formed in the N-type epitaxial silicon layer separated from each other, and P-type lower isolation layers and P-type upper isolation layers are formed between the P-type well regions. Then a charge transfer MOS transistor is formed in each of the P-type well regions. The P-type single crystalline silicon substrate is biased to a ground potential or a negative potential.

Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P+-type buried layer abutting on a bottom of the P-type well region and an N+-type buried layer partially overlapping with the P+-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.

Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and a P-type well region is formed in the second epitaxial silicon layer. A P+-type buried layer is formed abutting on a bottom of the P-type well region, and an MOS transistor is formed in the P-type well region. The MOS transistor has a first source layer N+S of high impurity concentration, a first drain layer N+D of high impurity concentration and a second source layer N?S and/or a second drain layer N?D of low impurity concentration, which is diffused deeper than the first source layer N+S of high impurity concentration and the first drain layer N+D of high impurity concentration.

Abstract: A latch up in a charge pump device is prevented as well as a withstand voltage of an MOS transistor used in the charge pump device is increased with this invention. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer separated from each other. A P-type isolation layer is formed between the P-type well regions. A P+-type buried layer is formed abutting on a bottom of each of the well regions, an N+-type buried layer is formed abutting on a bottom of the P+-type buried layer, and a transistor for charge transfer is formed in each of the P-type well regions.

Abstract: A three-stage switched capacitor DC-DC converter capable of generating an output boosted voltage in increments of less than power supply voltage. A first stage of the DC-DC converter comprises two capacitors and three switches, which alternate a connection of the two capacitors. The two capacitors are connected in series when charging by turning one of the switches ON, and are connected in parallel when discharging by turning the other two of the switches ON.

Abstract: An inrush current at beginning of operation of a charge pump circuit is reduced to prevent adverse effect on other circuits in a system. Charge transfer MOS transistors are connected in series. One end of each coupling capacitor is connected to each connecting point of the charge transfer MOS transistors. An output from each clock driver is applied on the other end of the respective coupling capacitor. Each clock driver includes a first clock driver and a second clock driver having higher driving capacity than the first clock driver. Each clock driver is controlled so that the first clock driver is put into operation at first and at the end of a predetermined elapsed time it is stopped and the second clock driver is put into operation.

Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P+-type buried layer abutting on a bottom of the P-type well region and an N+-type buried layer partially overlapping with the P+-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.

Abstract: P type well regions 31 and 32 are formed in N type well regions 21 and 22 respectively. The N type well regions 21 and 22 are formed separately each other. Charge transfer MOS transistors M2 and M3 are formed in the P type well regions 31 and 32 respectively. Thus, parasitic thyristor causing latch-up is nor formed.

Abstract: Malfunctioning is prevented with a charge-pump circuit which boosts a voltage in increments of less than power supply voltage. The charge-pump circuit has switches S1, S2 and S3 which connect capacitors 1 and 2 to a pumping node in series or in parallel accordingly to the following control steps. {circle around (1)} The switch S2 is turned ON to connect the capacitors 1 and 2 in series while the clock CLK is at L level. {circle around (2)} The switch S2 is turned OFF. {circle around (3)} The clock CLK is changed to H level. {circle around (4)} The switches S1 and S3 are turned ON to connect the capacitors 1 and 2 in parallel. {circle around (5)} The switches S1 and S3 are turned OFF. {circle around (6)} The clock CLK is changed to L level.

Abstract: A DC—DC converter capable of generating an output voltage in increments of less than power supply voltage Vdd is provided. A power supply voltage Vdd is provided to a three-stage switched capacitor type DC—DC converter. A first stage of the DC—DC converter comprises two capacitors C11 and C12 and switches 61, 62 and 63, that alternate a connection of the capacitors C11 and C12. The capacitors C11 and C12 are connected in series when charging by turning the switch 61 ON, while the capacitors C11 and C12 are connected in parallel when discharging by turning the switches 62 and 63 ON. Thus a boosted voltage of 3.5 Vdd is obtained from an output terminal 40.

Abstract: A latch up in a charge pump device is prevented as well as a withstand voltage of an MOS transistor used in the charge pump device is increased with this invention. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer separated from each other. A P-type isolation layer is formed between the P-type well regions. A P+-type buried layer is formed abutting on a bottom of each of the well regions, an N+-type buried layer is formed abutting on a bottom of the P+-type buried layer, and a transistor for charge transfer is formed in each of the P-type well regions.

Abstract: In a charge pump device, occurrence of a latch up can be prevented and current capacity can be increased. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, P-type well regions are formed in the N-type epitaxial silicon layer separated from each other, and P-type lower isolation layers and P-type upper isolation layers are formed between the P-type well regions. Then a charge transfer MOS transistor is formed in each of the P-type well regions. The P-type single crystalline silicon substrate is biased to a ground potential or a negative potential.

Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer. P+-type buried layers abutting on bottoms of the P-type well regions and N+-type buried layers abutting on bottoms of the P+-type buried layers and electrically isolating the P-type well regions from the single crystalline silicon substrate are formed. An MOS transistor is formed in each of the P-type well regions and a drain layer of the MOS transistor and each of the P-type well regions are electrically connected.

Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P+-type buried layer abutting on a bottom of the P-type well region and an N+-type buried layer partially overlapping with the P+-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.

Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and a P-type well region is formed in the second epitaxial silicon layer. A P+-type buried layer is formed abutting on a bottom of the P-type well region, and an MOS transistor is formed in the P-type well region. The MOS transistor has a first source layer N+S of high impurity concentration, a first drain layer N+D of high impurity concentration and a second source layer N−S and/or a second drain layer N−D of low impurity concentration, which is diffused deeper than the first source layer N+S of high impurity concentration and the first drain layer N+D of high impurity concentration.

Abstract: A DC-DC converter capable of generating an output voltage in increments of less than power supply voltage Vdd is provided.