Abstract: A DC-DC converter capable of generating an output voltage in increments of less than power supply voltage Vdd is provided.

Abstract: Charge transfer MOS transistors M1 and M2 at front two stages are constructed of an N-channel type, and charge transfer MOS transistors at rear two stages are constructed of an P-channel type. Inverting level shift circuits S1 and S2 and non-inverting level shift circuits S3 and S4, which can produces an intermediate potential are provided. Because of such a configuration, a charge pump circuit which can realize high efficiency and provide a large output current can be realized. In addition, the gate/source voltage Vgs (transistors are in the ON state) of the charge transfer MOS transistors can be uniformed to 2Vdd.

Abstract: A charge pump circuit of the Dickson type is provided, which circuit is characterized by clock drivers CD1 and CD2 for supplying clock pulses to coupling capacitors C1-C3. In other words, it is arranged in such a manner that the rising time and falling time of the clock pulses CLK and CLKB are extended to the extent that the outputs from the clock drivers CD1 and CD2 will not cause resonance.

Abstract: Charge transfer MOS transistors M1 and M2 at front two stages are constructed of an N-channel type, and charge transfer MOS transistors at rear two stages are constructed of an P-channel type. Inverting level shift circuits S1 and S2 and non-inverting level shift circuits S3 and S4, which can produces an intermediate potential are provided. Because of such a configuration, a charge pump circuit which can realize high efficiency and provide a large output current can be realized. In addition, the gate/source voltage Vgs (transistors are in the ON state) of the charge transfer MOS transistors can be uniformed to 2 Vdd.

Abstract: Malfunctioning is prevented with a charge-pump circuit which boosts a voltage in increments of less than power supply voltage. The charge-pump circuit has switches S1, S2 and S3 which connect capacitors 1 and 2 to a pumping node in series or in parallel accordingly to the following control steps.

Abstract: Provided are level shift circuits S1-S4 to on/off-control a charge-transfer MOS transistor M1-M4 depending upon a clock pulse, and a branched charge pump circuit BC branched from an intermediate stage of a charge pump circuit to output a positive boost voltage. By using each-staged output V4, V5 of the branched charge pump circuit BC as a high-potential power to the level shift circuit S3, S4, the charge-transfer MOS transistors M1-M4 of the charge pump circuit when turning on are made in the gate-to-source voltages to nearly a constant value.

Abstract: The charge-pump circuit has at least first and second MOS transistors for charge transfer M1 and M2 connected in series, first and second capacitors 1 and 2, a clock driver 3 supplying clock to one end of the second capacitor 2, first switching means S2 for connecting the first and second capacitors to a pumping node in series, and second switching means S1 and S3 for connecting the first and second capacitors to the pumping node in parallel The clock driver 3 changes the state of clock when both of the first and second switching means turn off.

Abstract: A charge-pump circuit has means biasing electrical potential of a substrate of a MOS transistor for control M2 so that forward direction current does not flow substantially through a,parasitic diode Dp1. In the concrete, the substrate of the substrate of a MOS transistor for control M2 is biased by voltage of a connecting point of the substrate of a MOS transistor for control M2 and a capacitor 1 at the case that the substrate of a MOS transistor for control M2 is P-channel type. Thus, it is prevented that a parasitic diode is biased to forward direction in a charge-pump circuit carrying out voltage fluctuation with lower voltage step than power source voltage Vdd so as to carry out normally charge-pump operation.

Abstract: P type well regions 31 and 32 are formed in N type well regions 21 and 22 respectively. The N type well regions 21 and 22 are formed separately each other. Charge transfer MOS transistors M2 and M3 are formed in the P type well regions 31 and 32 respectively. Thus, parasitic thyristor causing latch-up is nor formed.

Abstract: A charge-pump circuit comprising diodes D1 and D2, which are connected in series; capacitors C1A and C1B, which are connected to the juncture of the diodes D1 and D2; a clock driver 11, for supplying a clock to the capacitor C1B; and switches S1, S2 and S3, which are used to connect the capacitors C1A and C1B to the juncture of the diodes D1 and D2 in series or in parallel, consonant with the voltage level of the clock, wherein a boosted voltage is output by the diode D2.

Abstract: A charge pump circuit of the Dickson type is provided, which circuit is characterized by clock drivers CD1 and CD2 for supplying clock pulses to coupling capacitors C1-C3. In other words, it is arranged in such a manner that the rising time and falling time of the clock pulses CLK and CLKB are extended to the extent that the outputs from the clock drivers CD1 and CD2 will not cause resonance.

Abstract: The charge-pump circuit has at least first and second MOS transistors for charge transfer M1 and M2 connected in series, first and second capacitors 1 and 2, a clock driver 3 supplying clock to one end of the second capacitor 2, first switching means S2 for connecting the first and second capacitors to a pumping node in series, and second switching means S1 and S3 for connecting the first and second capacitors to the pumping node in parallel. The clock driver 3 changes the state of clock when both of the first and second switching means turn off.

Abstract: A charge-pump circuit has means biasing electrical potential of a substrate of a MOS transistor for control M2 so that forward direction current does not flow substantially through a parasitic diode Dp1. In the concrete, the substrate of the substrate of a MOS transistor for control M2 is biased by voltage of a connecting point of the substrate of a MOS transistor for control M2 and a capacitor 1 at the case that the substrate of a MOS transistor for control M2 is P-channel type. Thus, it is prevented that a parasitic diode is biased to forward direction in a charge-pump circuit carrying out voltage fluctuation with lower voltage step than power source voltage Vdd so as to carry out normally charge-pump operation.

Abstract: A charge-pump circuit comprising diodes D1 and D2, which are connected in series; capacitors C1A and C1B, which are connected to the juncture of the diodes D1 and D2; a clock driver 11, for supplying a clock to the capacitor C1B; and switches S1, S2 and S3, which are used to connect the capacitors C1A and C1B to the juncture of the diodes D1 and D2 in series or in parallel, consonant with the voltage level of the clock, wherein a boosted voltage is output by the diode D2.

Abstract: Charge transfer MOS transistors M1 and M2 at front two stages are constructed of an N-channel type, and charge transfer MOS transistors at rear two stages are constructed of an P-channel type. Inverting level shift circuits S1 and S2 and non-inverting level shift circuits S3 and S4, which can produces an intermediate potential are provided. Because of such a configuration, a charge pump circuit which can realize high efficiency and provide a large output current can be realized. In addition, the gate/source voltage Vgs (transistors are in the ON state) of the charge transfer MOS transistors can be uniformed to 2 Vdd.