Abstract: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN disposed along a direction D1 when a direction from a first side which is a short side of the integrated circuit device toward a third side opposite to the first side is a direction D1 and a direction from a second side which is a long side of the integrated circuit device toward a fourth side opposite to the second side is a direction D2. At least one of the circuit blocks on both ends of the circuit blocks CB1 to CBN is a scan driver block for driving a scan line. Or, the scan driver block SB is disposed along the direction D1 on the side of the first to Nth circuit blocks in the direction D2.

Abstract: An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a high-speed interface circuit block HB which transfers data through a serial bus using differential signals, and a circuit block other than HB. The high-speed interface circuit block HB is disposed as an Mth circuit block CBM (2?M?N?1) of the circuit blocks CB1 to CBN.

Abstract: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.

Abstract: An integrated circuit device includes: first to Nth circuit blocks CB1 to CBN disposed along a direction D1, the circuit blocks CB1 to CBN includes a data driver block DB. A data driver DR included in the data driver block DB includes Q driver cells DRC1 to DRCQ arranged along a direction D2, each of the driver cells outputting a data signal corresponding to image data for one pixel. When a width of each of the driver cells DRC1 to DRCQ in the direction D2 is WD, each of the circuit blocks CB1 to CBN has a width WB in the direction D2 of “Q×WD?WB<(Q+1)×WD”.

Abstract: An integrated circuit device includes a driver macrocell in which a plurality of circuit blocks are integrated into a macrocell. The driver macrocell includes a data driver block DB for driving data lines, a memory block MB which stores image data, and a pad block PDB in which pads for electrically connecting output lines of the data driver block DB with the data lines are disposed. The data driver block DB and the memory block MB are disposed along a direction D1, and the pad block PDB is disposed on the D2 side of the data driver block DB and the memory block MB.

Abstract: An integrated circuit device, including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines; and the memory block MB includes a memory cell array, a row address decoder RD, and a sense amplifier block SAB.

Abstract: An integrated circuit device includes a data driver block for driving data lines. The data driver block includes a plurality of subpixel driver cells, each of which outputs a data signal corresponding to image data of one subpixel. When a direction along the long side of the subpixel driver cell is a direction D1 and a direction perpendicular to the first direction is a direction D2, the subpixel driver cells are disposed in the data driver block along the direction D1 and the direction D2. Pads are disposed on the D2 side of the data driver block. A rearrangement wiring region for rearranging the order of pull-out lines of output signals from the subpixel driver cells is provided in the arrangement region of the subpixel driver cells.

Abstract: An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a logic circuit block LB, a grayscale voltage generation circuit block GB, data driver blocks DB1 to DB4, and a power supply circuit block PB. The data driver blocks DB1 to DB4 are disposed between the logic circuit block LB and the grayscale voltage generation circuit block GB, and the power supply circuit block PB.

Abstract: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN disposed along a direction D1, a first interface region provided on the D2 side of the circuit blocks CB1 to CBN, and a second interface region provided on the D4 side of the circuit blocks CB1 to CBN. The circuit blocks CB1 to CBN include a data driver block DB and a circuit block other than the data driver block DB. When the widths of the first interface region, the circuit blocks CB1 to CBN, and the second interface region in the direction D2 are respectively W1, WB, and W2, the integrated circuit device has a width W in the direction D2 of “W1+WB+W2?W<W1+2×WB+W2”.

Abstract: An integrated circuit device includes a scan driver block SB which generates a control signal for driving a scan line, a pad PDt electrically connected with the scan line, and transistors pDTrt and nDTrt of which a connection node DNDt is electrically connected with the PDt pad and which are push-pull connected between a high-potential-side power supply and a low-potential-side power supply. The transistors pDTrt and nDTrt are gate-controlled based on the control signal from the scan driver block SB. The pad PDt is disposed in an upper layer of at least one of the transistors pDTrt and nDTrt so that the pad PDt overlaps part or the entirety of at least one of the transistors pDTrt and nDTrt.

Abstract: An integrated circuit device includes: first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The first to Nth circuit blocks CB1 to CBN includes a logic circuit block LB which sets grayscale characteristic adjustment data; and a grayscale voltage generation circuit block GB which generates grayscale voltages based on the set adjustment data. The logic circuit block LB and the grayscale voltage generation circuit block GB are disposed adjacent to each other along the direction D1.

Abstract: A step-down circuit is provided that comprises a clock control circuit which provides a plurality of clock signals having a frequency determined based on a control signal; a charge pump circuit which reduces a first potential applied to a first terminal and then provides a second potential from a second terminal by switching the connection of a plurality of capacitors in sync with a plurality of the clock signals output from the clock control circuit; and a comparator which produces the control signal to be supplied to the clock control circuit by comparing the second potential to a reference potential.

Abstract: A semiconductor integrated circuit is provided comprising a first amplifier circuit which receives a first potential and then supplies a current to an output terminal; a second amplifier circuit which receives a second potential and then absorbs a current from the output terminal; and a control circuit which controls the second amplifier circuit so as to allow the second amplifier circuit to be activated subsequently to a predetermined period of time that elapses after the first amplifier circuit is activated.

Abstract: A semiconductor integrated circuit comprises a storage device that receives an input of data representative of an image to be displayed on a display apparatus and stores the data in a manner corresponding to a plurality of signal electrodes of the display apparatus, and outputs the stored data from a plurality of output terminals, a signal generation device that generates a plurality of signals to be supplied to the plurality of signal electrodes of the display apparatus based on data input through a plurality of input terminals, and outputs the same from a plurality of output terminals, and a selection device that selects data input from the plurality of output terminals of the storage device according to a selection signal that is externally input, and supplies the same to the plurality of input terminals of the signal generation device.

Abstract: A step-down circuit is provided that comprises a clock control circuit which provides a plurality of clock signals having a frequency determined based on a control signal; a charge pump circuit which reduces a first potential applied to a first terminal and then provides a second potential from a second terminal by switching the connection of a plurality of capacitors in sync with a plurality of the clock signals output from the clock control circuit; and a comparator which produces the control signal to be supplied to the clock control circuit by comparing the second potential to a reference potential.

Abstract: A semiconductor integrated circuit is provided comprising a first amplifier circuit which receives a first potential and then supplies a current to an output terminal; a second amplifier circuit which receives a second potential and then absorbs a current from the output terminal; and a control circuit which controls the second amplifier circuit so as to allow the second amplifier circuit to be activated subsequently to a predetermined period of time that elapses after the first amplifier circuit is activated.

Abstract: A power supply circuit is equipped with a first amplification path 10 in which a first potential is input and that supplies current to an output terminal when a control signal is in a first state; a second amplification path 20 in which a second potential is input and that absorbs current from the output terminal when a control signal is in a second state; an intermediate potential forming circuit that forms a third potential between the first potential and the second potential; and a comparison circuit 30 that compares the third potential with a potential at the output terminal to form a control signal and supplies the same to the first and second amplification paths.

Abstract: A semiconductor integrated circuit comprises a storage device that receives an input of data representative of an image to be displayed on a display apparatus and stores the data in a manner corresponding to a plurality of signal electrodes of the display apparatus, and outputs the stored data from a plurality of output terminals, a signal generation device that generates a plurality of signals to be supplied to the plurality of signal electrodes of the display apparatus based on data input through a plurality of input terminals, and outputs the same from a plurality of output terminals, and a selection device that selects data input from the plurality of output terminals of the storage device according to a selection signal that is externally input, and supplies the same to the plurality of input terminals of the signal generation device.

Abstract: A power supply circuit is equipped with a first amplification path 10 in which a first potential is input and that supplies current to an output terminal when a control signal is in a first state; a second amplification path 20 in which a second potential is input and that absorbs current from the output terminal when a control signal is in a second state; an intermediate potential forming circuit that forms a third potential between the first potential and the second potential; and a comparison circuit 30 that compares the third potential with a potential at the output terminal to form a control signal and supplies the same to the first and second amplification paths.